Converting this schematic to verilog code, compile unsuccessful

Question

Below is the full code. I would just like to implement the schematic below into Verilog code. Just a little confused if, I can write the combinatorial logic and sequential logic in one always block or not. Secondly, the sensitive list will need to clock impulses and input changes. This is a hand solved solution but now I would like to take it into Verilog and implement it in Verilog and see output.

module Q4a(
input x,
 input clock,
output z
);
reg z; 
reg y1,y2;
reg d1,d2;
//wire x;
//wire clock;

always @(x,y1,y2)
begin
d1=(~x)&y2;
d2=x;
z=x&y1; 
end

always @(clock)
begin 
//y1<=(~x)&y2;
//y2<=x;
//z<=x&y1;
y1<=d1;
y2<=d2;

end
endmodule

Answer 1

x and z have special meaning in Verilog, it would be best to use some thing else for variable names.

module Q4a(
 input x,
 input clock,
 output reg z //Just declare as reg here
);

reg y1,y2;
reg d1,d2;

// Use automatic sensitivity list
always @* begin
  d1=(~x)&y2;
  d2=x;
  z=x&y1; 
end

//Filp-flops use `posedge` to make edge sensitive
always @(posedge clock) begin 
  y1<=d1;
  y2<=d2;
end

endmodule

This compiles in vcs on EDA Playground. But to review I would write as :

module Q4a(
 input      x,
 input      clock,
 output reg z
);

reg y1,y2;

always @* begin
  z = x & y1; 
end

always @(posedge clock) begin 
  y1 <= ~x & y2;
  y2 <= x;
end

endmodule

Answer 2

It is not neccessary to use always begin ... end always, you can use direct assign statement to write combinational circuit.

See below code:

module Q4a (
             input wire x,
             input wire clock,
             input wire rst_n,
             output wire z
        );

wire d1;
reg  y1;
reg  y2;

assign d1 = ~x & y2;
assign z  =  x & y1;

always @ (posedge clock or negedge rst_n)
begin
  if(rst_n) begin
    y1 <= 1'b0;
    y2 <= 1'b0;
  end else begin
    y1 <= d1;
    y2 <= x;  // x is d2 too.
  end
end

endmodule

Or you can also do something like that too,

assign z  =  x & y1;

always @ (posedge clock or negedge rst_n)
begin
  if(rst_n) begin
    y1 <= 1'b0;
    y2 <= 1'b0;
  end else begin
    y1 <= ~x & y2;
    y2 <= x;  // x is d2 too.
  end
end