Access a Parameter from different module in verilog

0
votes

I'm new to verilog and I have following question,

package pkg;
   parameter WIDTH = 6;
endpackage

module mod1 #(parameter PAR = 10)(in1,clk,out1); 
   import pkg::*;
   localparam FOO = 10; 
   input in1,clk;
   output out1;
   assign out1 = in1;
endmodule
module mod2 (in1,clk,out1);
   logic a1[WIDTH:0];
endmodule

I have imported package pkg in module mod1 and can I use parameter WIDTH (defined in pkg) in module mod2as in above code?

I'm trying to understand the scopes of verilog. Can someone please explain this.

1
verilogsystem-verilog

1 Answers

2
votes

No. An import statement is only local to the block it appears in. Basically from the point it appears in the source, to the end word. In this case, the endmodule.