Redefining a parameter in verilog

Question

I'm new to verilog and I got a question.

Can I initializing a parameter in global scope and reinitializing it module scope.

parameter GLOB_FOO = 5;
module mod2 (in1,clk,out1);
   parameter GLOB_FOO = 7;
   input in1,clk;
   output out1;
   assign out1 = in1;
endmodule

In this code I have initialized parameter GLOB_FOO twise in global scope and in module scope.

I looked in the Language Reference Manual as well. But couldn't find the answer since there are a lot of details.

Is This kind of parameter reinitializing is valid in verilog?

dave_59 dave_59 · Accepted Answer · 2017-05-17T06:24:56

You have re-declared GLOB_FOO inside the module mod2, not re-initialized it. That means you have two parameters, one in the compilation unit scope with the value 5, and one in mod2 with the value 7. The declaration inside mod2 hides the declaration of the outer compilation unit. $unit:: can be used to access the outer declaration.

parameter GLOB_FOO = 5;
module mod2 (input in1,clk, output out1);
   parameter GLOB_FOO = 7;
   initial begin
         $display(GLOB_FOO); // displays 7
         $display($unit::GLOB_FOO); // displays 5
     end
endmodule

You can override the value of the parameters declared inside a module when instantiating it.

parameter GLOB_FOO = 5;
module mod2 (input in1,clk, output out1);
   parameter GLOB_FOO = 7;
   initial begin
         $display("%m %d %d", GLOB_FOO, $unit::GLOB_FOO);
endmodule
module top;
  bit A,B, C, CLK;
  mod2 #(3) inst1 (A,CLK,B);
  mod2 #(.GLOB_FOO(4)) inst2 (A,CLK,C);
endmodule

This displays

#top.inst1           3           5
#top.inst2           4           5

Redefining a parameter in verilog

1 Answers