I want to split a verilog program in a module that will be called from a top. This is a counter that displays the output,and every bit.
module file1(output reg b3,
output reg b2,
output reg b1,
output reg b0,
output reg[3:0]y);
reg clock;
initial begin
clock=0;
b0=0;
b1=0;
b2=0;
b3=0;
y=0;
forever #5 clock= ~clock;
end
always @(posedge clock)
begin
y=y+1;
b0=y[0];
b1=y[1];
b2=y[2];
b3=y[3];
end
endmodule
This is how I split the program in a module called by top. MODULE
module modul(input reg clock,
output reg b3,
output reg b2,
output reg b1,
output reg b0,
output reg[3:0]y
);
always @(posedge clock)
begin
y=y+1;
b0=y[0];
b1=y[1];
b2=y[2];
b3=y[3];
end
endmodule
TOP
`timescale 1ns/1ps
module testare_modul;
reg clock; wire clock1;
reg b3;
reg b2;
reg b1;
reg b0;
reg [3:0]y;
modul lol(
.clock(clock),
.y(y),
.b3(b3),
.b2(b2),
.b1(b1),
.b0(b0)
);
initial begin
clock=0;
b0=0;
b1=0;
b2=0;
b3=0;
y=0;
forever #5 clock= ~clock;
end
endmodule
I have 0 errors when compilling but when I try to simulate I get Illegal output or inout port connection.I am new to these language and I would appreciate your help a lot!
