Connect all modules in scheme by massive of wires. Verilog

Question

I have some modules in my scheme and I want to connect it by massive of wires. How it look in my mind:

When come changes of variable some_trigger in top level module, in this moment top level module send signal by input_output_wire in module a1-> module a1 make some stuff -> module a1 send too module a2 by the massive_input_output_wire[0] -> module a2 make some stuff -> a2 send by next wire in the massive massive_input_output_wire[1] to module a3 -> a3 make some stuff -> send to a4 by massive_input_output_wire[2] and so on...

module a(
input_output_wire;
);
input input_output_wire;
output input_output_wire;
always @(posedge input_output_wire)
begin
     if(input_output_wire) begin
         ....
             make some stuff
         ....
     end
end
end module


`include "a.v"
module top_level(
clk,
rst,
some_trigger
);
input clk, rst, some_trigger;
parameter NUM_OF_MODULES_A = 5;

wire massive_input_output_wire[0:NUM_OF_MODULES_A];

a a1(.input_output_wire(massive_input_output_wire[0]));
a an(.input_output_wire(massive_input_output_wire[NUM_OF_MODULES_A-1]));
genvar i;
genarate
        for(i=1;i<NUM_OF_MODULES_A-2; i = i + 1)
        begin : modules_a
            a modules_a(
            .(input_output_wire(massive_input_output_wire[i]))
            );
        end
endgenerate


always @(posedge some_trigger)
begin
     if(some_trigger) 
         massive_input_output_wire[0] = 1;
end
endmodule

Sorry: I don't understand what you are asking. Please can you add more explanation? — Matthew Taylor
Wires are not like variables in programing languages. They do not chain assignments with last one wins. The drive concurrently which often results in Xs. You should not use assign or force statements to assign a wire within an always block (I'm guessing that is what you are currently doing). — Greg
@MatthewTaylor ok, I want to connect all my modules(a1,a2,....an) in this logic : output wire from a1(massive_input_output_wire[0]) must go to input of a2. Output wire from a2(massive_input_output_wire[1]) must go to input of a3 .. output wire from a[n-1](massive_input_output_wire[n]) must go to input a[n]. The question is how correctly write the code for generate modules (modules_a) and for modules that I wrote without generate a1 and an — Anton
@Greg thanks you, I understand my mistake, but my problem now is not in this. — Anton
Module a should have at least two ports: an input and an output. a inst_a( .output_wire(massive_input_output_wire[i]), .input_wire(massive_input_output_wire[i-1]) ); — Greg

Mekala hanumanth reddy Mekala hanumanth reddy · Accepted Answer · 2017-03-17T18:19:01

As you said in your explanation, each module taking one signal and making some stuff and giving another signal to next module to make some another stuff.

To this your module should contain two ports
Like...

module a (input_wire,output_wire);
input input_wire;
output reg out_wire;
always
begin
Make some stuff
End 
Endmodule

Next in top module you instantiate like below

Module top(input_wire,output_wire,another );

Input input_wire ;
Output output_wire [0:3]

Make some stuff
 a a1(input_wire [0],output_wire [0]);
 a a2 (output_wire [0],output_wire [1]);
 a a3 (output_wire [1],output_wire [2]);
 Intantiations

 Endmodule

This may help you, if I understand your explanation correctly

Connect all modules in scheme by massive of wires. Verilog

1 Answers