Synthesis-able 'X' or invalid input detection system in Verilog

Question

I am trying to make a synthesis-able Verilog code, which can detect 'x' or invalid inputs. Basically, x is not synthesis-able so I am avoiding x. I am trying to read inputs at every clock cycles and if it is 0 or 1 then I am loading into a new register. Here is the code;

always@(posedge clk)
begin
    if(in & gate_check == 0 | in & gate_check == 1)
    begin
        load_input_8 <= {in,load_input_8[8:1]}; 
    end
end

So, I am loading new inputs into load_input_8 register, after checking validity of input data. By the way, gate_check has value of 1 i.e. `gate_check = 1.

But this is only storing value of 1 into load_input_8. No 0 is being stored in load_input_8. And circuit is also having strange behavior in loading inputs. Here is the picture of simulation; Thank you.

Answer 1

Thanks to @Laleh for helping in this issue. There was issues of (). Here is correct code;

always@(posedge clk)
begin
    if((in & gate_check) == 0 | (in & gate_check) == 1)
    begin
        load_input_8 <= {in,load_input_8[8:1]}; 
    end
end