Which value will be used in an always block?

Question

Here is a verilog code: (This code is not for synthesis)

`timescale 1 ns / 1 ns

module test;
    reg r1, r2, r3, r4;
    reg clk_at_time, clk_from_clk;


    // Initialize signals 
    initial begin
      r1 <= 1;
      r2 <= 0;
      clk_at_time <= 1;
      #200
      $finish();
    end


    // Generating simple a clock (period time is 10ns)  (as expected)
    always #5
        clk_at_time <= ~clk_at_time;


    // Generating a clock based on the clk_at_time.
    // This clk_from_clk is always equals the clk_at_time (as expected)
    always @ clk_at_time
        clk_from_clk <= clk_at_time;


    // r1 and r2 inverted at all posedge event. (as expected)
    // r3 is constant 0 (as expected)
    always @(posedge clk_at_time) begin
        r1 <= r2;
        r2 <= r1;
        r3 <= clk_from_clk;
    end


    // r4 is constant 1  ???!!!??? HOW ???!!!???
    always @(posedge clk_from_clk) begin
        r4 <= clk_at_time;
    end

endmodule

And the waveform of the simulation:

In the code there are two clock: first is the traditional clock generated by time always #5 the second is generated by this clock always @ clk_at_time The two clocks are always equal (as expected)

The strange thing that if I use the clk_from_clk in clk_at_time's block the previous value will be used of clk_from_clk. (OK), BUT if I use the clk_at_time in clk_from_clk's block the NEW value will be used of clk_at_time.

EDIT

Clarify: See the waveform: clk_from_clk and clk_at_time are equals always.

See code: r3 and r4 are analog:

r3 is in clk_at_time's block and driven by clk_from_clk
r4 is in clk_from_clk's block and driven by clk_at_time

So if clk_from_clk and clk_at_time are really the same r3 and r4 should have be equal always. BUT See the waveform: r3 is always 0 and r4 is always 1

HOW? What is the rule?

The strange thing that if I use the clk_from_clk in clk_at_time's block the previous value will be used of clk_from_clk. (OK), BUT if I use the clk_at_time in clk_from_clk's block the NEW value will be used of clk_at_time. What? Are you talking about substituting always @(posedge clk_at_time) for always @(posedge clk_from_clk)? Please could you edit your question to make this clearer? — Matthew Taylor
Can you make your question more clear? And also change the names of clk_from_clk and clk_at_time, as both are very confusing with each other. — Karan Shah
I answered your same question of at Electronics StackExchange. it is usually recommended to inform of a cross post within the StackExchange network. — Greg

Alper Kucukkomurler Alper Kucukkomurler · Accepted Answer · 2017-03-02T06:07:47

I don't know the exact answer but I want to share an opinion, thinking from the simulations viewpoint. I'm writing this as an answer instead of a comment because it won't fit in comments.

I think this has to do with the finite element analysis nature of the simulation. At each time-step of the simulation, the simulator solves the circuit component by component. And since your clk_from_clk is derived frın clk_at_time the simulator will always evaluate the latter first.

The r4 is evaluated after clk_from_clk so it will always have the value of 1. As for ther3 it will be evaluated at the change of clk_at_time and simultaneous with clk_from_clk and have its previous value.

Which value will be used in an always block?

1 Answers