How to use Tcl/Tk with VHDL

Question

I am new to both VHDL and Tcl/Tk. Straight to question: I want to know how to use Tcl/Tk in Modelsim. Suppose I do not know anything in Tcl/Tk, but I have the following VHDL code for a full adder to start with. What can I do with it using Tcl/Tk and what steps should I take.I am using Quartus Prime Standard Edition and Modelsim with Altera Cyclone FPGA.

 LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 USE ieee.std_logic_signed.all;
 ENTITY adder IS
--H&G are 8 bit inputs 
--M is 8-bit output 

PORT (carryin : IN STD_LOGIC;
        X,Y   : IN STD_LOGIC;
        S         : OUT STD_LOGIC;
        carryout: OUT STD_LOGIC);
 END adder;

 ARCHITECTURE Behaviour OF adderk IS 
--SIGNALS ARE VARIABLES THAT WE WILL SIGN OUR OUTPUT VARIABLES TO
Signal Sum : STD_LOGIC;
BEGIN 

    Sum <= X XOR B XOR carryin;
    carryout <= X AND B AND carryin AND (A XOR B);
    M<=Sum;
END Behaviour;

Arkoudinos Arkoudinos · Accepted Answer · 2017-02-04T21:45:12

TCL is just another way to interact with the ModelSim environment. Instead of doing things in GUI using your mouse, TCL gives you the flexibility of creating scripts for simulating and evaluating your design. You can take a look here, which I think you will find very useful.

How to use Tcl/Tk with VHDL

1 Answers