Data types in VHDL

Question

I am trying to implement a filter in VHDL. All input vectors and output vectors are in signed 16 bits (1.15 format, the first bit is a sign bit). I plan to declare all signals / variables as STD_LOGIC / STD_LOGIC_VECTOR type(s). All the calculations will be based on 2's complement.

There are packages (in IEEE) such as std_logic_1164 (std_logic types & related functions), std_logic_arith (arithmetic fuctions), std_logic_signed (signed arithmetic functions), and std_logic_unsigned (unsigned arithmetic functions).

In order to achieve all the 2's complement operations in this filter implementation based on types of STD_LOGIC / STD_LOGIC_VECTOR, which library should I use? Should I use both std_logic_signed.ALL and std_logic_1164.ALL?

I would recommend using signed (and unsigned) vectors and associated operators from numeric_std. If you're not familiar with this package, Wikipedia has a brief article. — rtx13

Tricky Tricky · Accepted Answer · 2020-05-19T06:19:08

std_logic_(un)signed and std_logic_arith are NOT standard VHDL packages. They were written by synopsys nearly 30 years ago and never part of the VHDL standard.

The VHDL standard packages appropriate here would be numeric_std from VHDL 93 (for unsigned and signed types) or numeric_std_unsigned for arithmetic with std_logic_vector (from VHDL 2008). Also available in VHDL2008 is the fixed_pkg, that allows the user to define and do arithmetic with fixed point packages. eg:

signal a,b : sfixed(0 downto -15); -- 1.15 signed fixed 
signal c   : sfixed(1 downto -15);

....

a <= to_sfixed(0.12345, a);
b <= to_sfixed(-0.54321, b);

c <= a + b;

This is fixed point, 2s compliment, integer arithmatic.

Data types in VHDL

1 Answers