Building AXI4-Stream (VHDL) around Verilog core. Unable to resolve warnings

Question

I'm trying to build an AXI4-Stream IP block out of an encryption core named chacha. My AXI4-Stream wrapper is in VHDL, and the chacha core is in Verilog.

Here is the chacha core.

I have looked around a lot in the forums and it seems using VHDL and Verilog like this should not be a problem, but I still can't get it to work.

This is what I have done so far:

Use the "Create and package IP" tool in Vivado to generate an AXI4-Stream block with inputs and outputs.
Edit it to include the IP I want.
Change the type under File Groups to Mixed in both Synthesis and Simulation see Figure 1.
Added two new bus interfaces - One Reset and one Clock to connect to my RST and CLK.

Figure 1

This removed all errors and most of the warnings. The only warnings left are four cases of this error:

[IP_Flow 19-991] Non-synthesizable or non-simulation file ’hdl/chacha_qr.v’ found in file group ’VHDL Synthesis’. You may want to add it to the xit utility file group.

I tried ignoring this, and used the block anyway with a MicroBlaze to see if it would work. Unfortunately when Vivado is running the implementation it throws a BLACK BOX error:

[DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell ’design_1_i/axis_chacha_0/U0/chacha_inst’ of type ’design_1_i/axis_chacha_0/U0/chacha_inst/chacha_core’ has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

Here is the link for the project. I know that all the connections to the chacha core are not finished yet, but I don't think that the warnings come from there.

Did you forget to declare a VHDL component for the Verilog module by any chance? — andrsmllr
No I did declare the component but I found out how to get around the problem now. I will post an answer to my own question shortly. Thank you any way! — tore

tore tore · Accepted Answer · 2016-12-05T10:59:40

I got some help to solve this. Apparently you get rid of the warnings if you add two new file group (Synthesis and Simulation) in standard instead of advanced. And then move the files there in stead of once under the advanced category. Now the warnings are gone and so is the black box error.

Changed to standard instead of advanced

Building AXI4-Stream (VHDL) around Verilog core. Unable to resolve warnings

1 Answers