Can I use Vivado block design clock frequencies in my VHDL?

Question

I'm building a design in Vivado and am wondering if I can use the block diagram clock frequencies in my HDL.

I want to take the FREQ_HZ that the block diagram knows about and propagates as part of DRC, and feed it into my custom IP blocks (using a VHDL generic). This is so that I can do things like set up internal counts to generate delays in microseconds, baud rates, etc.

I could do this with a manual Customisation Parameter, but that would need manual maintaining and be prone to error.

This question doesn't appear to present a specific VHDL programming question. — user1155120
It probably applies similarly to Verilog, but I am using and familiar only with VHDL. But if you mean this is more of a vendor tool question - yes it is. — blueshift

Timmy Brolin Timmy Brolin · Accepted Answer · 2015-04-11T09:55:51

I think TCL might be your only option here. Make a TCL script which runs as a part of your build process, and copy the FREQ_HZ attribute to your generic.

Can I use Vivado block design clock frequencies in my VHDL?

1 Answers