Simulating VHDL 2008 unconstrained array type in Vivado 2017.1

Question

I have the following type

type VECTOR_ARRAY_TYPE is array(natural range <>) of std_logic_vector;

which I use in my entity as follows:

entity mux is

  generic (
    sel_width  : positive := 2;
    data_width : positive := 3
  );

  port (
    d   : in  VECTOR_ARRAY_TYPE(2**sel_width - 1 downto 0)(data_width - 1 downto 0);
    sel : in  std_logic_vector(sel_width - 1 downto 0);
    q   : out std_logic_vector(data_width - 1 downto 0)
  );

end mux;

I am using Vivado 2017.1 and have marked the files as VHDL 2008. The files synthesize perfectly well, but I get the following error when trying to Run Simulation:

ERROR: [XSIM 43-4187] File "/project_dir/sources_1/new/alu_data.vhd" Line 42 : The "Vhdl 2008 Unconstrained Array Type as Subtype in Array Type Definition" is not supported yet for simulation.

The line number it is referring to is the type definition above.

Is it the case that the error is correct, and that unconstrained array types cannot be used for simulation? Or is there a setting somewhere which I need to change to configure the simulator differently?

Thanks.

prolly correct. You can always try the newest version (v2017.4). — JHBonarius
Your usage is correct. You need to submit it as a bug to Xilinx. It is 10 years after this was standardized in IEEE and 12 years after it was standardized by Accellera. Can't really claim they have not had sufficient time to implement it. — Jim Lewis
Elaboration is completely different for synthesis which maps to binary types and simulation. User Guide 901 (Synthesis) lists unconstrained element types as supported (Ch. 8 VHDL-2008 Language Support, Supported VHDL-2008 Features, Types). User Guide 900 (Logic Simulation) Table C-1 hasn't been changed in 2017. That pretty much leaves you with ALDEC or Modelsim for a simulator supporting an unbound array type with an unconstrained element subtype (IEEE Std 1076-2008 5.3.2 Array types, 5.3.2.1 General). — user1155120
@JHBonarius "Demonstrated demand" is what some EDA vendors also call market driven. Hence, we all need to submit bug reports to demonstrate the demand. In fact, what we need is a website with standardized test cases and a method to automatically submit them to vendors - that way one person can generate the report and each person who wants that feature to work can submit it - hence demonstrating demand for the feature. — Jim Lewis
@JHBonarius Don't loose hope. Competing things like SystemVerilog should be mostly done. Our time slot is now. Submit those bugs. Complain loudly about broken features. — Jim Lewis

JHBonarius JHBonarius · Accepted Answer · 2017-12-27T14:48:07

So your question is about a software tool, which has an extensive on-line documentation. So you should look on the website. http://www.xilinx.com --> support --> documentation --> Development tools --> Hardware development --> Vivado Design Suite --> User Guides. Et voila: UG900 - Vivado Design Suite User Guide: Logic Simulation v2017.4

Appendix C: VHDL 2008 Support in Vivado Simulator

The Vivado® simulator supports the subset of VHDL 2008(IEEE 1076-2008). The complete list is given in Table C-1.

[partial] Table C-1:

VHDL-2008 STD and IEEE packages precompiled, including new fixed and float packages, unsigned bit etc.

Simplified sensitivity list

Matching Relational Operators

Unary Reduction Logic Operators

Simplified Case Statement

Array / Bit Logic Operators

Array / Bit Addition Operators

Enhanced Bit String Literals

Conditional and selected sequential statements

Protected type

Keyword ‘parameter’ in procedure declaration

Array element resolution function in subtype definition

Block comments

Predefined array types

Type passed as Generic

Hierarchical references to signal

Expression in port map

Reading output port

Note: Other features that are not mentioned in the above table, are not supported by Vivado Simulator.

Simulating VHDL 2008 unconstrained array type in Vivado 2017.1

1 Answers