how to do post synthesis simulation in vivado

Question

I am using the Vivado Design Suite 2017.2 I have a vhdl design and a testbench added to a simulation set.

Behavioral simulation runs nicely. If I synthesize the design and click on "Run Simulation - Post synthesis functional" it still runs without errors. Yet I am not sure if it really does simulate my synthesized design or if it is just doing the 'old simulation' once again. The point is that I know that for post synthesis simulation a new vhdl/verilog file gets created that represents the netlist. Yet I did not make any changes to the testbench, saying I did not instantiate the new file explicitely. The question now is whether this happens automatically.

I have looked through the tutorials but could not find an answer.

Any help will be appreciated.

Answer 1

If you want to be sure your are simulation the real net list you can 'browse' the simulation hierarchy (Like you normally do to e.g. to add signals to the wave window). A the bottom level of your browsing tree you should only find FPGA primitives.