Xilinx ISE Post Place and route simulation using behavioral modules

Question

I have created a verilog module A, and a testbench for this module called A_tb.

The testbench contains instances of other modules (B,C) that are connected to an instance of A in the testbench.

I can correctly generate post synthesis timings for A, and want to run a post PnR simulation using testbench A_tb.

Running a behavioral simulation on the testbench works, and produces correct results.

Running a post-PnR simulation gives an error that modules B,C can't be found. Is it possible to simulate these modules behavioral-ly just to generate stimulus for the post PnR timings model of A ?

EDIT: Synthesis and post-PnR timing using XST, simulation using isim.

How and where are you setting $sdf_annotate?, you might have the wrong scope selected — Greg
$sdf_annotate is for applying post-PnR timing information to the simulation. When I saw post-PnR I accidentally assumed it was a timing annotation related problem. It can generate a similar error messages. — Greg

toolic toolic · Accepted Answer · 2013-11-11T20:41:17

You should be able to run simulations with the same B/C modules in both cases.

For your behavioral simulation that works, are modules A, B and C all in the same file? If so, you should split modules B and C out into a separate file from module A, then load in the new file with modules B and C.

Xilinx ISE Post Place and route simulation using behavioral modules

1 Answers