0
votes

I am writing a Verilog code for calculating the number of digits in a decimal number. In the code below I have initialised the value of c to be equal to a. I was able to get the simulation results correctly but unable to syntesise and the error is due to 'c=a'. How can I get rid of the error ? Is there any other logic to calculate the number of digits ?

Error: [Synth 8-3380] loop condition does not converge after 2000 iterations 

Code :-

module numdigits(a,b);
parameter n=100;
input [0:n-1] a;
output reg [0:n-1]b;   //THIS MODULE COUNTS THE NUMBER OF DIGITS IN DECIMAL FORM
reg [0:n-1] d,c;
always @(*)
begin 
    d=0;
    for(c=a;c>0;c=c/10)
    begin
    d=d+1;
    end
    b=d;
end 
endmodule
1
I am not having any issues with your module. Perhaps its a testbench or tool issue? See: edaplayground.com/x/24e3 - Hida
@Hida I am using vivado software and why do we need a test bench to synthesize the code? Its mainly for simuation, right? - Vineeth Ananthula
I agree it didn't properly answer your question. However I would like to point out that you should always simulate your RTL to reduce time spent debugging on FPGA/synthesis feedback. - Hida
I'll give a hint: something like this will static unroll for you d=0; b=0; for(c=1;c<{n{1'b1}};c=10*c) begin if(...) begin b = ... ; end d=d+1; end fill in the ...s. - Greg
@Greg if(c>a) begin:abc b=d; disable abc end d=d=+1; end. Is this right? - Vineeth Ananthula

1 Answers

0
votes

In order for a for loop to be synthesisable, it must be static: that is, the maximum number of iterations round the loop must be fixed. It might seem that there is a maximum number of iterations of your loop, given that a has a fixed number of bits, but remember that your synthesiser doesn't simulate your code, so it cannot tell that.

You need to refactor your code; you need to write it in such a way so that the maximum number of loop iterations is fixed. In other words, the number of iterations of the loop must be fixed, but you can jump out early if you wish (using the disable statement).