VHDL CLOCK SEQUENCE Q3

Question

i have to create a VHDL sequence thats takes only a clock input and out puts a 5 led sequence see picture am i correct in thinking that using the std_logic_vector i can then connect each vector output to a single LED in order to create this sequence or am i miss interpreting the use of the std_logic_vector?

the code i have used is

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all; -- i have used this package as my CLK-CNT signal    counts in integer format rather than binary and i am performing an ADD sum of   the CLK_CNT


entity REG_LED is
 PORT(CLK:      IN  std_logic;              -- CLK input
     LEDS:      Out std_logic_vector (4 downto 0) ); -- initialise output
End REG_LED;

ARCHITECTURE behavioral OF REG_LED IS
SIGNAL CLK_CNT:     integer range 0 to 9:= 0; -- initailise comparison signal used for counting clock pulses.
 -- This signal will be used by the program to recognise where in the sequnce the program is and thus determine the next state required for the sequence.
BEGIN

    CLK_Process:    PROCESS (CLK)   -- begin the CLK_CNT Process
    BEGIN 

    if rising_edge(CLK) Then
        if CLK_CNT = 8 then 
            CLK_CNT <= 0; -- this resets the clock pulse count to 0
        else
            CLK_CNT <= CLK_CNT + 1 ; -- used to count each clock pulse upto the reset 
        End if;
-- this process has been kept seperate to the LED output process in order to isolate the event from the output process and limit the possiblities of errors         
    END IF;

    END PROCESS ;

    LED_PROCESS: Process (CLK_CNT) -- LED Outputs based on Temp count

    BEGIN -- begin the output sequence 

        Case CLK_CNT is 
-- i use a case statement to compare the value of the CLK_CNT signal and produce the required LEDS output 
-- this ensures the 
            When 0 =>
                LEDS <= "11111"; -- S0 when clock count is 0
            When 1 =>
                LEDS <= "00001"; -- S1 when clock count is 1
            When 2 =>       
                LEDS <= "00001"; -- S2 when clock count is 2
            When 3 =>
                LEDS <= "11111"; -- S3 when clock count is 3
            When 4 =>
                LEDS <= "00000"; -- S4 when clock count is 4
            When 5 =>
                LEDS <= "11111"; -- S5 when clock count is 5
            When 6 =>
                LEDS <= "00100"; -- S6 when clock count is 6
            When 7 =>
                LEDS <= "01010"; -- S7 when clock count is 7
            When 8 =>
                LEDS <= "10001"; -- S8 when clock count is 8 this is the final clock count state

            When others => 
                LEDS <= "11111"; -- Restart Sequence

        End Case;               

    End Process;
END behavioral;

i have simulated the waveform and it produces the 5 outputs as required by the sequence but can this output beused to drive 5 different leds or will it just be a 5 bit word that is output of one port? im new to VHDL so any help would be appreciated

If you connect one LED to each bit of the port, it'll drive 5 LEDs. — user_1818839

Wizongod Wizongod · Accepted Answer · 2016-10-29T03:43:27

Your code looks fine, and if your simulation indicates it is functioning according to what you need then you are almost good to go.

A std_logic_vector is really a number of wires (bus). You have to think about what it physically means, because that's what really happens when you program an FPGA. So yes, you can split up (or breakout) the bus into individual lines. This can be done as such:

signal LED_LINE_0 : std_logic;
signal LED_LINE_1 : std_logic;
LED_LINE_0 <= LEDS(0);
LED_LINE_1 <= LEDS(1);

...and so on. This rips out one wire at a time. You can also split a bus into smaller buses by ripping out multiple wires at a time. e.g.

signal small_bus_1 : std_logic_vector(1 downto 0);
signal small_bus_2 : std_logic_vector(1 downto 0);
signal big_bus : std_logic_vector(3 downto 0);

small_bus_1 <= big_bus(3 downto 2);
small_bus_2 <= big_bus(1 downto 0);

You can then write in your constraints file (or use the GUI in the IDE of your FPGA brand) to specify which pin on the FPGA you'd like each of these std_logic to be assigned to (that drives the LED you need).

VHDL CLOCK SEQUENCE Q3

1 Answers