How do you simulate a VHDL file in Altera ModelSim when another VHDL file is required to successfully accomplish the task?

Question

The first VHDL is used to make 26 LEDs rotate 0 to 26. To do so would need a clock signal at 10 hz and 1 hz. The only available clock is 50Mhz. The second VHDL file is to slow down the available signal to 1 and 10hz. I use a .do file to run the simulation to make a waveform. The 50Mz clock shows up fine but both 1hz and 10hz are flatlined. Those two require the second VHDL file. Is it required to have both files in the simulation to make this work, because ModelSIm only allows the selection of 1 VHDL file per simulation?

In short one file has the bulk of the rotating led code and the other is essentially a header file to accomplish a task needed for the main file. I want to simulate the first but some signals seem to need the second file during the simulation but you cannot include it.

You haven't supplied enough detail. FPGA vendors manage 'projects' with which design files are associated, resulting in all the analyzed design units residing in the same work library. It sounds like the second VHDL file is not present (analyzed into) in the work library - unbound when instantiated, likely because it hasn't been associated with the 'project'. You've also not mentioned a test bench (which may have been automatically generated producing your, and mentioned in, the do file). — user1155120

Daniel Kho Daniel Kho · Accepted Answer · 2014-09-15T02:35:42

Yes, if you would like to simulate both files, then both must be added (or compiled) into your simulation environment, using vcom for ModelSim for example. It's good if you could post some sample code in your first and second files.

I had the impression that your second file is a frequency divider, since you mentioned in the first paragraph that all it does is to slow down the 50-MHz signal to 1Hz and 10Hz. However, I'm having doubts after reading your second paragraph, which says "one file has the bulk of the rotating led code and the other is essentially a header file to accomplish a task needed for the main file".

Well, if you would like to simulate your entire design, and your LED logic is in one file, while the frequency divider is in another, you still need to write testbench code (to supply clock and reset for example). This testbench encapsulates (instantiates) your entire design, and would be closer in concept to what you called the "header file". Usually, we'll write the testbench as a separate file, which means you would have 3 files - not a hard rule, but it's typically done this way.

So, first file will be your LED "rotator, second file would be your frequency divider, and the third file will be your testbench.

Another thing. Dividing 50 MHz down to 1 Hz or 10 Hz takes up a lot of simulation time, both in the amount of time for you to wait for meaningful results, and amount of storage your computer needs to store the waveforms. Perhaps you're seeing "flatlines" because you haven't simulated enough points to see any change in the 1-Hz or 10-Hz waveforms. If you like to see at least 1 cycle of 10 Hz for example, you'll need to simulate at least 0.2 us worth of simulation points. Check the end of your waveform to see how much simulation time it took to simulate your last run.

Another reason could be you haven't yet written your testbench, and have not yet supplied any clock into your design?

In any case, it would be nice if you could post up some of your code.

How do you simulate a VHDL file in Altera ModelSim when another VHDL file is required to successfully accomplish the task?

1 Answers