Simple oscillator in VHDL

Question

I've just started with VHDL, and I have a problem understanding how exactly process operates. Here is an example of a simple oscillator:

timer_1Hz: process(clk) is
    variable timer : integer := 0;
    constant period : integer := 50E6;
begin
--if rising_edge(clk) then
    timer := (timer+1) rem period;
    if (timer=0) then
        led <= not led;
    end if;
--end if;
end process timer_1Hz;

clk is an input (clock) signal with 50 MHz frequency, and 50% duty cycle.

Now, as I understand it, the process timer_1Hz will be triggered on any change in the clk signal, whether that be a transition from 0 to 1, or from 1 to 0.

I expected from the above example to flash LEDs with a frequency of 0.5 Hz, since the rising_edge test was commented out. In other words, I expected that the body will be triggered two times in a single clock period, on a rising and a falling edge. However, that doesn't seem to work, i.e., LEDs are never turned on.

If I include the rising_edge test, LEDs blink with a 1 Hz frequency, just as I expected.

Can someone please explain what am I missing in the unexpected case.

Fpga registers cannot be triggered on both rising and falling edge. You need to use only one edge. — JHBonarius

vipin vipin · Accepted Answer · 2017-11-04T15:22:55

The code will not work without the rising edge part you removed. It might work in simulation, but not in a real fpga board. Why? Because sensitivity list is (mostly) important for simulation and not(so much) for synthesis.

For synthesis purpose, you have to always think about the hardware you would be implementing. In a practical sense, a process is NOT "run" when certain events occur.

If you really want 0.5 Hz output, just use 25E6 instead of 50E6 with the original code..

Simple oscillator in VHDL

1 Answers