So I've upgraded from Vivado 2015.4 to 2016.2. I use Vivado to compile the simulation files for the encrypted IPs. When I launch Modelsim 10.4, a new error appears:
sources_1/ip/output_buffer/sim/output_buffer.v(289): Module 'fifo_generator_v13_1_1' is not defined.
The first thing I noticed is that in my project flow, generated simulation files are now verilog which could be the source of my problems since I usually simulated VHDL.
First I compile the various libraries such as the fifo_generator library:
compile_simlib -simulator questa
Then I generate the simulation files:
import_files -norecurse -fileset sources_1 cgen/output_buffer/output_buffer.xci
upgrade_ip [get_ips output_buffer]
generate_target simulation [get_files output_buffer.xci]
export_simulation -simulator questa -of_objects [get_files output_buffer.xci]
exec echo exit | vsim -c -do top/top.srcs/sources_1/ip/output_buffer_sim/questa/compile.do -modelsimini modelsim.ini
My modelsim.ini file then maps these libraries:
[Library]
fifo_generator_v13_1_1 = msim/fifo_generator_v13_1_1
output_buffer = top/top.srcs/sources_1/ip/output_buffer/questa
Finally my .tcl script will build the project and add the simulation files:
vlog top/top.srcs/sources_1/ip/output_buffer/sim/output_buffer.v
Yet when I launch my project, it complains it cannot find the fifo_generator. Any ideas why this might be?
EDIT
As requested, the generated compile.do:
vlib work
vlib msim
vlib msim/xil_defaultlib
vlib msim/xpm
vlib msim/fifo_generator_v13_1_1
vmap xil_defaultlib msim/xil_defaultlib
vmap xpm msim/xpm
vmap fifo_generator_v13_1_1 msim/fifo_generator_v13_1_1
vlog -work xil_defaultlib -64 -sv \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_base.sv" \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dpdistram.sv" \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_dprom.sv" \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sdpram.sv" \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_spram.sv" \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_sprom.sv" \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_memory/hdl/xpm_memory_tdpram.sv" \
vcom -work xpm -64 \
"/software/CAD/Xilinx/2016.2/Vivado/2016.2/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work fifo_generator_v13_1_1 -64 \
"../../output_buffer/fifo_generator_v13_1_1/simulation/fifo_generator_vlog_beh.v" \
vcom -work fifo_generator_v13_1_1 -64 \
"../../output_buffer/fifo_generator_v13_1_1/hdl/fifo_generator_v13_1_rfs.vhd" \
vlog -work fifo_generator_v13_1_1 -64 \
"../../output_buffer/fifo_generator_v13_1_1/hdl/fifo_generator_v13_1_rfs.v" \
vlog -work xil_defaultlib -64 \
"../../output_buffer/sim/output_buffer.v" \
vlog -work xil_defaultlib "glbl.v"
It copies the modelsim.ini file and then you can run one or all three of these commands. All I want to do actually is compile so I have the object which can be used by my simulation later, which is the output_buffer.v file which is created.
# RUN_STEP: <compile>
compile()
{
# Compile design files
source compile.do 2>&1 | tee -a compile.log
}
# RUN_STEP: <elaborate>
elaborate()
{
source elaborate.do 2>&1 | tee -a elaborate.log
}
# RUN_STEP: <simulate>
simulate()
{
vsim -64 -c -do "do {simulate.do}" -l simulate.log
}
# STEP: setup
setup()
{
case $1 in
"-lib_map_path" )
if [[ ($2 == "") ]]; then
echo -e "ERROR: Simulation library directory path not specified (type \"./output_buffer.sh -help\" for more information)\n"
exit 1
fi
copy_setup_file $2
;;
"-reset_run" )
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
;;
"-noclean_files" )
# do not remove previous data
;;
* )
copy_setup_file $2
esac
# Add any setup/initialization commands here:-
# <user specific commands>
}
