"after" not working in Modelsim

Question

I am trying to make a behavorial model of a Serial Adder in Modelsim.

So, in the design I am trying to pass the Carry_out to the Carry_in after one clock cycle.

The design is:

one bit, each from two n-bit numbers enter the adder along with the carry.

Initially the carry is 0 but in the next clock cycle the carry_out from the addition of the previous bits are again passed as the carry_in and addition is done with the next two bits, one from each number.

Here is the code:

library ieee;

use ieee.std_logic_1164.all;

entity serial_adder is

    port (a,b: in std_logic;
        s: out std_logic;
        cin,cout: inout std_logic);
end serial_adder;

architecture serial_adder_arch of serial_adder is
begin
    process(a,b,cin,cout)
    begin
    if (a='0' and b ='0' and cin ='0')
    then s <='0';
         cout <='0';
    elsif (a='0' and b ='0' and cin ='1')
    then s <='1';
         cout <='0';
    elsif (a='0' and b ='1' and cin ='0')
    then s <='1';
         cout <='0';
    elsif (a='0' and b ='1' and cin ='1')
    then s <='0';
         cout <='1';
    elsif (a='1' and b ='0' and cin ='0')
    then s <='1';
         cout <='0';
    elsif (a='1' and b ='0' and cin ='1')
    then s <='0';
         cout <='1';
    elsif (a='1' and b ='1' and cin ='0')
    then s <='0';
         cout <='1';
    elsif (a='1' and b ='1' and cin ='1')
    then s <='1';
         cout <='1';
    end if;
    cin <= cout after 50 ps;
    end process;

end serial_adder_arch;

After simulation, I am seeing that the delay that I am giving using 'after' is not working. I am getting no delay and the cout is not getting assigned to cin

Answer 1

What is your simulator time resolution? It defaults to 1ns, and time delays will be rounded to the resolution.

Try vsim -t 50ps to change the resolution to 50ps.

Answer 2

Even if you get this code working in simulation, it wouldn't synthesis, because of the wait for statement.

See the below serial adder code.

library ieee;
use ieee.std_logic_1164.all;

--serial adder for N bits. Note that we dont have to mention N here. 
entity serial_adder is
    port(Clk,reset : in std_logic; --clock and reset signal
            a,b,cin : in std_logic;  --note that cin is used for only first iteration.
            s,cout : out std_logic  --note that s comes out at every clock cycle and cout is valid only for last clock cycle.
            );
end serial_adder;

architecture behav of serial_adder is

--intermediate signals.
signal c,flag : std_logic := '0';

begin

process(clk,reset)
--we use variable, so that we need the carry value to be updated immediately.
variable c : std_logic := '0'; 
begin
if(reset = '1') then --active high reset
    s <= '0';
    cout <= c;
    flag <= '0';
elsif(rising_edge(clk)) then
    if(flag = '0') then
        c := cin;  --on first iteration after reset, assign cin to c.
        flag <= '1';  --then make flag 1, so that this if statement isnt executed any more.
    end if; 
    s <= a xor b xor c;  --SUM
    c := (a and b) or (c and b) or (a and c);  --CARRY
end if;
end process;

end behav;

If you like it, then there is testbench code and explanation on this link.