VHDL Syntax error near "procedure".Formal crcreg of mode inout must have an associated actual

Question

I want to test this package with a simple testbench. I have tried to keep the object classes, modes, types and also signal names same. Still the following syntax errors persist.

Line 36: Syntax error near "procedure".
Line 36: Formal crcreg of mode inout must have an associated actual

Line 36: Formal has no actual or default value.

Line 38: Syntax error near "package".

Line 38: Expecting type void for .

1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.std_logic_unsigned.all;
5--use std.textio.all;
6
7 library work;            -- make library visible
8 use work.crc_function.all;   -- make package visible
9           
10
11 package crc_package is
12    procedure UpdateCRC(
13        signal CRCREG : inout STD_LOGIC_VECTOR (7 downto 0);
14        signal INBYTE : in STD_LOGIC_VECTOR (7 downto 0)
15        );
16 end crc_package;
17
18 package body crc_package is
19
20      -- type required for the CRC generation
21      type CrcValues_T is array (0 to 8) of STD_LOGIC_VECTOR(7 downto 0); 
22  
23      procedure UpdateCRC(
24      signal CRCREG : inout STD_LOGIC_VECTOR (7 downto 0);
25    signal INBYTE : in STD_LOGIC_VECTOR(7 downto 0)) is 
26    variable tmp : CrcValues_T;
27    begin
28      tmp(0) := CRCREG;
29      -- generate the logic for the next CRCREG byte using a
30      loop
31      for i in 1 to 8 loop
32          tmp(i) := NextCRCVal(tmp(i-1), INBYTE(i-1));
33      end loop;
34      -- tmp 8 is the final value
35      CRCREG <= tmp(8);
36  end procedure UpdateCRC; --
37
38 end package body crc_package;

the testbench has the following signals declared

architecture behavioral of crc_function_tb is 
    signal clk          : std_logic := '0';
    signal reset        : std_logic := '0';
    signal CRCREG       : inout STD_LOGIC_VECTOR (7 downto 0):= (others => '0');
    signal INBYTE       : in STD_LOGIC_VECTOR(7 downto 0) := (others => '0');

the procedure is called in the following test process block in testbench

101 test: process (clk, reset)
102 begin
103     wait for clk_period * 20;
104     CRCREG_loop: for i in 1 to 32 loop
105         INBYTE_loop:  for j in 1 to 8 loop
106                         wait for clk_period * 1;
107                         
108                          UpdateCRC(CRCREG, INBYTE);
109                             
110                    -- out1:= UpdateCRC(std_logic_vector(inp1), std_logic_vector(inp2));
111                         wait for clk_period * 5;
113                                 INBYTE <= INBYTE + 1;
114                 end loop;
115                 CRCREG <= CRCREG + 1;
116                 wait for clk_period * 1;
117                 end loop;
118 wait for clk_period * 20;
119 wait;
120 end process;

The code isn't a Minimal Complete and Verifiable example. It doesn't allow a person potentially answering to replicate your problem. Your error messages aren't complete and don't indicate which design unit they come from nor does your question. Your tool would have told you. This is first a a syntax problem. Line numbers would have to be stripped for someone using a VHDL analyzer/elaborator/simulator to replicate results. — user1155120

scary_jeff scary_jeff · Accepted Answer · 2016-09-02T13:47:48

29      -- generate the logic for the next CRCREG byte using a
30      loop

Your comment goes onto two lines; you need the comment indicator -- on both lines.

You have lines like use ieee.numeric_std.all;, but there should be an initial library ieee; for these to work.

You have use ieee.std_logic_unsigned.all;; you are not using anything from this, and are missing use ieee.std_logic_1164.all;

With these things fixed, your package compiles. Note that you did not include the code for crc_function, so I had to comment lines referencing that out.

VHDL Syntax error near "procedure".Formal crcreg of mode inout must have an associated actual

1 Answers