Verilog operation unexpected result

0
votes

I am studying verilog language and faced problems.

integer intA;
...
intA = - 4'd12 / 3; // expression result is 1431655761.
                    // -4’d12 is effectively a 32-bit reg data type

This snippet from standard and it blew our minds. The standard says that 4d12 - is a 4 bit number 1100. Then -4d12 = 0100. It's okay now.

To perform the division, we need to bring the number to the same size. 4 to 32 bit. The number of bits -4'd12 - is unsigned, then it should be equal to 32'b0000...0100, but it equal to 32'b1111...10100. Not ok, but next step.

My version of division: -4d12 / 3 = 32'b0000...0100 / 32'b0000...0011 = 1

Standart version: - 4'd12 / 3 = 1431655761

Can anyone tell why? Why 4 bit number keeps extra bits?

1
verilog

1 Answers

4
votes

You need to read section 11.8.2 Steps for evaluating an expression of the 1800-2012 LRM. They key piece you are missing is that the operand is 4'd12 and that it is sized to 32 bits as an unsigned value before the unary - operator is applied.

If you want the 4-bit value treated as a signed -3, then you need to write

intA = - 4'sd12 / 3 // result is 1