How to check data one cycle later in Verilog?

1
votes

At posedge of clock, if I get reset, I want to check that data is zero one cycle after reset. I am not able to figure out how can I check data one cycle after I get reset. This is what i came up with but i know it is wrong as I am checking for data in the same clock cycle that reset is high. Please can someone let me know how can I do this in verilog?

always @(posedge clk)
   if(reset)
      if(data == 0) 
         $display("ok");
      else 
         $display("error");
2
verilog

2 Answers

1
votes

There's an easy way to do this:

always @(posedge clk)
   reset_q <= reset;

always @(posedge clk)
   if(reset_q == 1) && (data == 0) 
      $display("reset ok");
   else 
      $display("reset error");

I put these in separate blocks to emphasize that one is a pipelining operating on the reset signal and the other is the checking logic, but they could live in the same always block.

0
votes

It seems that you don't want to try using always block on your testbench. It's a good idea to use forever loop in your testbench as an alternative to always block as it can have some flexibility in controlling your testbench.

Someone told me this: always block are for RTL design and forever loop are for RTL verification

You can try this instead:

initial begin
   forever begin    
      @(posedge reset); // wait for the rising edge of reset

      // reset has occured at this time.
      @(posedge clk); // delay for 1 clock cycle

      // check your data here
      if(data == 0) $display("ok");
      else $display("error");
   end
end