Unexpected delay in Verilog adder

Question

I have written some Verilog code for an adder with 10 inputs. After simulation I am getting the output with one extra clock delay. Why am I getting this delay?

`timescale 1ns/1ps

module add_10(z0,z1,z2,z3,z4,z5,z6,z7,z8,z9,clk,reset,o);
input [7:0] z0,z1,z2,z3,z4,z5,z6,z7,z8,z9;
input clk,reset;
output reg[15:0] o;
always @ (posedge clk or negedge reset)
begin
    if (!reset)
        o=16'b0000;
    else
        o = z0+z1+z2+z3+z4+z5+z6+z7+z8+z9;
end
endmodule

After asserting the reset, I am getting the output after one clock. But according to the code I wrote, it should come at the next posedge clk when reset=1.

I don't know the timing of your clock, but you are essentially stringing 10 8-bit adders in series. That will cause some delay. If you need precise timing, it would be better to store the result of the addition in a register and clock it out on the next cycle. — ThomasMcLeod
In the testbench i am declaring the generation of reset and after using non-blocking assignments also i am unable to get the correct output. So in what way i need to change my program to get the output as i discussed in the question. — user3178637

Jeff Mercado Jeff Mercado · Accepted Answer · 2014-01-22T05:48:55

It looks like it's working as it should to me.

I think you're misunderstanding how the reset signal is meant to be used. The reset signal should be kept high at all times. When it goes low, the output will be cleared immediately (it changes on the negative edge). When it goes high, the output will take on the sum of the inputs on the next clock cycle.

If you wanted to update on the positive edge of the reset signal, use the positive edge...

always @ (posedge clk or posedge reset)
...

Just beware that doing so will likely affect your minimum cycle times.

Unexpected delay in Verilog adder

3 Answers