how to design a flip flop that samples the input after 2 clock cycles using system verilog?

Question

the data is input in the first posedge clock but the output should present after 2 clock cycles.

i've tried using #delay but not quite getting it.

clk=0;
forever #10 clk = ~clk;
always @ (posedge clk) begin //synchronous rst
#60 q<=d;
end

A flip-flop can be thought of as (i) a one clock cycle delay, (ii) a one-bit memory or (iii) a sampling circuit. Given (i), you need 2 flip-flops, connected in series, with the Q output of the first connected to the D input of the second. — Matthew Taylor
thanks for answer....can designing a latch instead of flip flop can help in this ? — Ansuman Mishra

vinam vinam · Accepted Answer · 2020-05-19T19:25:52

One way to solve your problem would be to have 2 flip-flops.

reg q1, q2;
always @(posedge clk) begin
   q1 <= d;
   q2 <= q1;
end

Now, q2 will follow the input with a 2 clock-cycle latency, which is what you wanted.