Generic Multiplexer warning

Question

I created a generic multiplexer( on number of inputs and bits per input) in VHDL. I tested it and it works correctly but I get a width mismatch warning: Width mismatch. < output > has a width of 8 bits but assigned expression is 64-bit wide. This is the code of my generic MUX. Can anyone explain me why I get this warning? WHat's wrong with my code? My professor wants me to implement this without the use of process. Thanks

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use work.package_log.all;
use IEEE.NUMERIC_STD.ALL;

entity mux_generic is
 generic(N : natural :=8;
         M : natural := 8);
            -- N: number of inputs
            -- M: bit per input/output
Port ( input : in  STD_LOGIC_VECTOR (N*M-1 downto 0);
          sel: in STD_LOGIC_VECTOR (log2ceil(N)-1 downto 0);
       output : out  STD_LOGIC_VECTOR (M-1 downto 0));
end mux_generic;

architecture DataFlow of mux_generic is

begin

output <= input(M*(to_integer(unsigned(sel))+1) - 1 downto M*(to_integer(unsigned(sel))));

end DataFlow;

The function log2ceil is defined in this way:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package package_log is

    function log2ceil( n : natural) return natural;

end package_log;

package body package_log is

function log2ceil (N : natural) return natural is 
        variable i, j : natural;
     begin
        i := 0;
        j := 1;
        while (j < N) loop
            i := i+1;
            j := 2*j;
        end loop;
        return i;
     end function log2ceil;

end package_log;

Is this a synthesis or simulation warning? Why is it no error? Width mismatches should cause an failure. — Paebbels
And what tool reports the error, e.g. Altera Quartus Prime or other ? — Morten Zilmer
Do everybody's eyes a favour and declare sel of type natural range x to y; for suitable x,y... that string of unnecessary conversions is painful to look at! — user_1818839
It is a synthesize warning. WARNING: XST:1610. But I tried the bitstream on my Basys 2 and it works. I was wondering why I do get this warning message even if it works both in simulation and on the board. — Mazzola

Martin Zabel Martin Zabel · Accepted Answer · 2016-01-24T21:11:13

Please update to the lastest ISE version 14.7, if you haven't done so far. Then enable the new parser for your Spartan-3E FPGA:

Right click on Synthesize -> Process Properties.
Change property display level to "Advanced".
For property "Other XST Command Line Options" enter -use_new_parser yes.

Now the warning goes away. A new warning appears, just noting, that the new parser is not the default one. But, I didn't experienced a problem with this yet.

By the way, your multiplexer description is not yet efficient. Take at look at my other post, for different implementations and their effects on resource usage and timing analysis.

Generic Multiplexer warning

1 Answers