Stuck at synthesis for RAM block-> giving warning as Sourceless signal

Question

Below is the RAM Module, where i wish to read the coefficients value.

entermodule RAM_LP#( parameter width=8, length=16 )

(output reg [width*width-1:0]data_out,

input [width-1:0] address,

input clk,we);

// let the tools infer the right number of BRAMs

(* ram_style = "block" *)

(* synthesis, ram_block *)

reg [15:0] mem [0:65535];

parameter load_file = "generated/LP_coefficients.txt";

initial  
    begin
        $readmemh (load_file, mem);

end

 always @(posedge clk) begin

if (we) 

     data_out <= mem[address];
   end


endmodule

Giving warning and stuck at this point ->

WARNING:Xst:653 - Signal <mem> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.

Please guide me how to resolve this .

Declare data_out as [2*width-1:0]data_out instead of [width*width-1:0]data_out since your mem is of 16-bits width. and address as [length-1:0] address. — sharvil111
Please post the complete error message, it should include the signal name. The parameters of your module are useless, as long as the memory has a fixed size. — Martin Zabel

mcleod_ideafix mcleod_ideafix · Accepted Answer · 2016-01-01T12:44:23

You never write anything new to the RAM, so the symthesis tool warns you about this and treat this RAM as a ROM.

This portion of code:

always @(posedge clk) begin
  if (we) 
     data_out <= mem[address];
end

Reads current memory address when we is 1. I assume you want to write to the memory when we is 1, so it should be like this:

always @(posedge clk) begin
  if (we) 
     mem[address] <= data_in;
  data_out <= mem[address];
end

Being data_in an input port with data that you want to write into the memory. Note the clock cycle after the write operation, data_out will still have the old memory content. To have data_out to be updated if a write was performed, do like this:

always @(posedge clk) begin
  if (we) begin
     mem[address] <= data_in;
     data_out <= data_in;
  end
  else
    data_out <= mem[address];
end

Your module currently has no data_in port, so it describes a ROM, not a RAM, and in a ROM, this warning is harmless.

Stuck at synthesis for RAM block-> giving warning as Sourceless signal

1 Answers