SystemVerilog errors

0
votes

Error: (vlog-13069) C:\Modeltech_pe_edu_10.4a\examples\tb.sv(192): near "(": syntax error, unexpected '(', expecting ';' or ','.

I don't know what happened.Same code works well on Aldec.

program automatic process (dut_io.TB a);            
parameter CLK_CYCLE=40;
parameter num_data=16;
......


endprogram

process process_instance (dut_io.TB);    //here shows the error
1
system-verilog

1 Answers

2
votes

process is a built-in class in SystemVerilog. See IEEE Std 1800-2012 ยง 9.7 Fine-grain process control and Annex G.6 Process. Rename your process to a non-reserved word, for example myProcess.

The dut_io.TB in program automatic process (dut_io.TB a); should be an interface name (ex: my_interface)or interface name dot modport (ex: my_interface.my_modport. It should not be a hierarchical path to an instance of an interface.