Does not work as before Verilog initial construction in ModelSim Altera Edition 10.4

2
votes

Since version 10.4, start problem with initial block. Like this:

reg [31:0] init_ram[15:0];

initial begin
   init_ram[0] = 32'h1234_5678;
   init_ram[1] = 32'h8765_4321;
   ...
end

always_ff @(posedge clk)
   init_ram[addr] <= data;

Or

module test(
   input clk,
   ...
   output reg a
);

initial a = 1'b1;

always @(posedge clk)
   a <= ...;

ModelSim 10.4 error:

Error (suppressible): (vlog-7061) {path} Variable 'init_ram' driven in an always_ff block, may not be driven by any other process

In older versions all works well.

You don't know which ModelSim parameter should I change to fix it?

2
verilogsystem-verilogmodelsimintel-fpgaquartus

2 Answers

2
votes

One of the problems with the always_ff and always_comb constructs is that they are supposed to check the synthesizability during simulation, except that there is no standard for what is synthesizable. If the intent is that the initial blocks are just for simulation, then you will need to change the always_ff to always or change the initial block to use force/release instead.

0
votes

One idea for a work around to your problem is to add a reset signal and use it to initialize the value of a register.

Well, probably this would be a good way to give an initial value to your flip-flops.

This should be something like:

reg [31:0] init_ram[15:0];
input reset;

always_ff @(posedge clk) begin
   if (reset) begin
      init_ram[0] <= 32'h1234_5678;
      init_ram[1] <= 32'h8765_4321;
   end
   else begin
      init_ram[addr] <= data;

Or this:

module test(
   input clk,
   input reset,
   ...
   output reg a
);

always @(posedge clk) begin
   if (reset) begin
      a <= 1'b1;
   end
   else begin
      a <= ...;