If-else condition for n-bit number

Question

I want to design a ripple carry adder which will add n bit A and B number. Before adding I want to check whether any of the input is zero or not. If any value is zero, I want to return another input as output. My script is something similar to below-

module RCA #(parameter n=10) (input [n-1:0] A, input [n-1:0] B,output [n-1:0] R);

wire [n-1:0] r1;
wire [n:0] carry;
assign carry[0]=0;

genvar i;
generate
for (i=0;i<n;i=i+1) begin:ripple_block
FA fa(.a(p[i]),.b(q[i]),.s(r1[i]),.cout(carry[i+1]));
end
endgenerate

if (p==0) begin:a1
assign R=q;
end

if (q==0) begin:a2
assign R=p;
end

else begin:a3
assign R=r1;
end

endmodule

I am getting the error

"Elaboration time unknown or bad value encountered for generate if-statement condition 
expression. Please make sure it is elaboration time constant."

Please help me find the error in the script.

Thanks Farhana

sharvil111 sharvil111 · Accepted Answer · 2015-11-10T02:28:12

You have used if..else condition in a wrong manner. The if..else condition must be used in a procedural block. While here, it is used inside module directly.

The compiler was expecting if..else inside the generate block. But I guess this is not the intent of your code.

Just remove the conditions and use ternary operators (? :) instead. So, your code looks as follows:

module RCA #(parameter n=10) (input [n-1:0] A, input [n-1:0] B,output [n-1:0] R);
// ...
// ...
generate
//...
//...
endgenerate

//if (p==0) begin:a1
/***Use of ternary operator here***/
  assign R= (p==0) ? q : ((q==0) ? p : r1); 
// end

// if (q==0) begin:a2
// assign R=p;
// end
// 
// else begin:a3
// assign R=r1;
// end

endmodule

There can be other methods also. Using always_comb or always @(*) are some of the alternative. For more information on ternary operator and about your question, refer to this link. As always, SystemVerilog LRM 1800-2012 chapter 11 and 12 can be useful.

If-else condition for n-bit number

1 Answers