multi bit clock converged to single bit using type casting

Question

I tried to convert multiple bits to single bit using type casting method, but lint checker (LEDA) is not allowing [0:0] and points it as error. Does [0:0] means an array still?

Code used:

module xyz(
  input        x,
  input      rst,
  input      din,
  output reg dout
);

  logic [1:0] i_clk;
  logic [0:0]   clk;

  assign i_clk = logic'(x    );
  assign clk   = logic'(i_clk);

  always_ff @(posedge clk) begin 
    if (rst) 
      dout <= '0;
    else 
      dout <= din; 
  end

endmodule

LEDA Design checker command line:

leda -top xyz filename.v -config leda_config.tcl +v2k -sverilog

leda_config.tcl:

rule_deselect -all rule_select -rule W450

Error looks like:

 Multi-bit expression (e.g., a[2:0]) used as clock

What kind of error? I couldn't recreate it with software I use. — Qiu
Lint error(you can use any Linting tool) multi bit expression used as clock — Emman
logic is a System verilog defination , its not in verilog .Are you sure you are compiling with -sv ?? — chitranna
yes I am compiling with systemverilog switches here I am posted because its not allowing me to add systemverilog tag here. Not sure why it requires 1500 rep to post as systemverilog? — Emman
consider using LEDA Design checker, leda -top xyz filename.v -config leda_config.tcl +v2k -sverilog in config I am having rule_deselect -all rule_select -rule W450 I am sure spyglass too supports this Error looks like Multi-bit expression (e.g., a[2:0]) used as clock — Emman

dave_59 dave_59 · Accepted Answer · 2014-11-28T21:03:44

Many tools have problems with logic clk versus logic [0:0] clk. Technically, the former is a scalar variable and the latter is an array of one element, Unfortunately, many tools have incorrectly allowed you to make references to clk[0] or clk[0:0] even though it was declared as logic clk;, so the way tools react to the different declarations or references become muddled.

multi bit clock converged to single bit using type casting

1 Answers