Apology the title does not explain the question very well, I'll explain it in detail down below.
I'm new to verilog and got painfully stuck with my first lab assignment. One task is to make a 4*4 carry save multiplier, which is made of two types of multipliers, which are in turn made of full adders and AND gates, full adders are made of half adders. I built from the simplest half adders all the way up to the carry save multiplier.
two types of multipliers: http://i129.photobucket.com/albums/p205/Jack_Tianyu_Yang/Capture1_zpsf34b724c.png
hand-drawing of the carry save multiplier http://i129.photobucket.com/albums/p205/Jack_Tianyu_Yang/photo_zps905f2c13.jpg
The code for the carry save multiplier is here. I instantiated the two types of multipliers and use a lot of internal wires for connections. (I admit it's pretty naive but this is the best i can do for the time being, I'll keep practicing and get better at it.) My QUESTION is this: refer to the "hand-drawing" ,the most left module on the top row, you can see there are two ports---q0_out and q1_out, that are outputs of this multiplier module BUT not part of the outputs in the main output list. Actually, q0_out,q1_out,q2_out,q3_out and m0_out,m1_out,m2_out,m3_out are all not in the output list. They are actually the same value of q0 to q3 and m0 to m3,respectively. (This can be verified by the first image) When I synthesized the code I pasted below, Xilinx ISE gave me a bunch of same warnings saying for example :"Assignment to q3_out ignored, since the identifier is never used". When I ask the TA, he said I should "treat the 4*4 carry save multiplier as a black box and the only inputs are m3m2m1m0, q3q2q1q0 and the only output is p7p6p5p4p3p2p1. Outputs like q3_out are 'internal' and should not be presented in the final output list". I don't how to deal with this situation. As you can see, I simply assign q3 to q3_out because q3_out is the same value propagated all the way from q3.
Please feel free to comment on my codes (what to improve, what's a bad coding style) and ask me for more elaboration of the question, also, if possible, please please share some ideas of how to solve this problem. Thank you all in advance.
`timescale 1ns / 1ps
module multiplier44_OMG(
input m0,m1,m2,m3,q0,q1,q2,q3,
output p0,p1,p2,p3,p4,p5,p6,p7
);
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17,w18,w19,w20;
wire w21,w22,w23,w24,w25,w26,w27,w28,w29,w30,w31,w32,w33,w34,w35,w36,w37; //Internal wires
wire cin0,cin1,cin2,mk1_mul2_3; //These inputs are feeding into the carry save multiplier and are all zeroes.
wire q0_out,q1_out,q2_out,q3_out,m0_out,m1_out,m2_out,m3_out;
assign cin0=1'b0;
assign cin1=1'b0;
assign cin2=1'b0;
assign mk1_mul2_3=1'b0;// Inputs are assigned to zero.
assign q0_out=q0;
assign q1_out=q1;
assign q2_out=q2;
assign q3_out=q3;
assign m0_out=m0;
assign m1_out=m1;
assign m2_out=m2;
assign m3_out=m3;//THIS IS THE PART I DON'T KNOW HOW TO DEAL WITH
and (p0,m0,q0);
multiplier2 mul2_0(m1,m0,q0,q1,cin0,w1,w2,w3,w4,p1);
multiplier2 mul2_1(m2,m1,w1,w2,w3,w5,w6,w7,w8,w9);
multiplier2 mul2_2(m3,m2,w5,w6,w7,w10,w11,w12,w13,w14);
multiplier2 mul2_3(mk1_mul2_3,m3,w10,w11,w12,q0_out,q1_out,w15,w16,w17);
multiplier mul_0(w9,w4,q2,cin1,w18,w19,w20,p2);
multiplier mul_1(w14,w8,w18,w19,w21,w22,w23,w24);
multiplier mul_2(w17,w13,w21,w22,w25,w26,w27,w28);
multiplier mul_3(w15,w16,w25,w26,q2_out,w29,w30,w31);
multiplier mul_4(w24,w20,q3,cin2,w32,w33,m0_out,p3);
multiplier mul_5(w28,w23,w32,w33,w34,w35,m1_out,p4);
multiplier mul_6(w31,w27,w34,w35,w36,w37,m2_out,p5);
multiplier mul_7(w29,w30,w36,w37,q3_out,p7,m3_out,p6);
endmodule
It's does not feel any good staring at the code alone in the lab on a friday night.(Plus it's Spring festival.) I know my question is quite elementary, but even though I need help, GREAT help from the GREAT netizens.
