Asynchronous D FlipFlop synthesis

0
votes
 module dff_async(clk,r1,r2,dout);
 input clk,r1,r2;
 output reg dout;

  always@(posedge clk or negedge r1)
  begin

    if(r2)
      dout<=1'b1;
    else
      dout<=1'b0;
  end

 endmodule

The above code does not synthesize, and has error:

Assignment under multiple single edges is not supported for synthesis

enter image description here

The code should have been synthesized as shown in the above figure, according to my interpretation. I am not able to find the issue. What is stopping in synthesizing the code?

1
asynchronousverilogsynthesisflip-flop
Is that because, since we have two asynchronous signals in sensitivity list ie clk and r1, the tool is not able to identify which one should be the clock signal? either clk or r1 ? – VIJETH ANCHATGERI

1 Answers

1
votes

You need to asynchonously reset dout when r1 is low:

module dff_async (clk,r1,r2,dout);
    input clk,r1,r2;
    output reg dout;

    always @(posedge clk or negedge r1) begin
        if (!r1) begin
            dout <= 1'b0;
        end
        else begin
            dout <= r2;
        end
    end
endmodule

Note that the code for the mux has been simplified.