Verilog high impedance inout synthesis

Question

I generally don't use inout or high impedance states in verilog for synthesis (under the assumption that the internal logic ultimately has to implement it as standard CMOS 2 state logic anyways).

However, I'm finding a lot of verilog that is destined for synthesis that looks like the following:

module top(
    inout signal1,
    inout signal2
);

    submodule sub1 ( 
        //outputs from sub1
        signal1, 
        signal2
    );
    submodule sub2 ( 
        //outputs from sub2
        signal1, 
        signal2
    );

endmodule

Where signal1 and signal2 are only driven to either 1'b0 or 1'bz and they are declare as open-drain ports in the contraints file.

Do most synthesis tools support synthesizing this? I'm targeting a lattice CPLD and it seems to work fine, but I'm curious if other tools synthesize things like this ok?

Do you typically have to explicitly tell the tools to pull-up the signal? or is this generally not necessary ( I cannot find any mention of pull-ups in the code I'm looking at)

PrzemekS PrzemekS · Accepted Answer · 2019-04-25T07:16:19

FPGA is equipped with configurable IO banks and depending on how tool is instructed with constraints file you might have an ‘enable’ at your disposal. For driving the open-drain bus generally tri-state buffers are used where (1) output signal (directed towards the bus) is tied to constant zero, (2) enable signal (connected to enable of tri-state buffer) is considered as actual control logic that provides switching between high-Z (generated by physical Bus implementation, i.e. pull-up resistor) and strong 0 (that is sourced from our output signal), (3) input signal (directed towards our internal logic (used for data acquisition and bus arbitration).

I’ve never seen signals driven with 1’bz in RTL code in any of commercial projects i’ve been involved in and my recommendation would be to avoid it as I believe there is always more conventional way to approach it (solely with logic 1’b1 and 1’b0 in combination with tri-state buffer)

Verilog high impedance inout synthesis

1 Answers