SPARTAN SP601: Why are there two pins associated with one clock?

Question

I'm using the Spartan 6 (SP601 Evaluation Board) and was previously using the X2 27MHz Oscillator Clock. However, according to the user manual, there is a faster 200 MHz oscillator (differential) soldered onto the board. I would like to use it, but I am confused why it has two pins associated to it.

Provided below is the table with the clocks and their respective pins on the board. I am currently using the X2 with only one pin, so I have one input called "clk" that is connected to that pin. Could someone explain why there are two pins, "N" and "P" for the U5? How would I include and use this clock in my user constraints file?

Answer 1

From the SP601 Hardware User Guide, 8. Clock Generation:

The SP601 has one 2.5V LVDS differential 200 MHz oscillator (U5) soldered onto the board and wired to an FPGA global clock.

From the Wikipedia page Differential signaling, the section Advantages, suitability for use with low-voltage electronics:

The electronics industry, particularly in portable and mobile devices, continually strives to lower supply voltage to save power and reduce emitted electromagnetic radiation. A low supply voltage, however, reduces noise immunity. Differential signaling helps to reduce these problems because, for a given supply voltage, it provides twice the noise immunity of a single-ended system.

To see why, ...

Under High-voltage differential signaling:

...
The generic term High-voltage differential signaling describes a variety of systems. Low-voltage differential signaling or LVDS, on the other hand, is a specific system defined by a TIA/EIA standard.

So the clock is an LVDS clock differentially signaled, the purpose of Low Voltage signaling to reduce power. Differential to add noise immunity.

This doesn't appear to be a programming question and the answer can be determined by simple research.