I'm very new to Zedboard. I'm writing a counter in VHDL, and try to implement it on the Zedboard Zynq 7000 XC7Z020-1 CSG484CES EPP.
When I allocate the pin, I want to have a clock. But it seems wrong to allocate "clk" to a user switch. So I looked up the document ZedBoard_HW_UG_v1_1.pdf.
In chapter 2.5, it says the following:
The EPP’s PS subsystem uses a dedicated 33.3333 MHz clock source, IC18, Fox 767- 33.333333-12, with series termination. The PS infrastructure can generate up to four PLL-based clocks for the PL system. An on-board 100 MHz oscillator, IC17, Fox 767-100-136, supplies the PL subsystem clock input on bank 13, pin Y9.
But when I allocate NET "clk" LOC = Y9;, it seems doesn't work! I can't find where the clk is! There suppose to be a button or something that I can control, right?
The warning is this:
PhysDesignRules:2452 - The IOB q<1> is either not constrained (LOC) to a specific location and/or has an undefined I/O Standard (IOSTANDARD). This condition may seriously affect the device and will be an error in bitstream creation. It should be corrected by properly specifying the pin location and I/O Standard.
every pin has a warning like this. And here is my ucf file:
NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "q[6]" LOC = T22;
NET "q[5]" LOC = T21;
NET "q[4]" LOC = U22;
NET "q[3]" LOC = U21;
NET "q[2]" LOC = V22;
NET "q[1]" LOC = W22;
NET "q[0]" LOC = U19;
NET "d[6]" LOC = G22;
NET "d[5]" LOC = H22;
NET "d[4]" LOC = F21;
NET "d[3]" LOC = H19;
NET "d[2]" LOC = H18;
NET "d[1]" LOC = H17;
NET "d[0]" LOC = M15;
NET "clk" LOC = Y9;
NET "clr" LOC = T18;
NET "alm" LOC = U14;
Where can I find a document explain what I need to do? And if Y9 is the correct choice for clock, how can I know the upper edge has come? since there's no botton that I can operate? A lot of thanks!!!
