I'm designing a Master-Slave D Flip Flop implementation in ModelSim. After compiling (Compile > Compile All), I'm typing vsim into the console, and the only error thrown is
# vsim
# Start time: [time]
# Error loading design
Is there any way of having vsim be more verbose with what is going wrong? Or, alternately, could someone tell me what I'm doing wrong?
For reference, my code is below:
methods.v
module dFlipFlop(
D,
Clk,
En,
Q
);
input D, Clk, En;
output Q;
reg Q;
always @ (posedge Clk)
if(~En) begin
Q <= 1'b0;
end else begin
Q <= D;
end
endmodule
module masterSlaveDFF(
D,
Clk,
En,
Q
);
input D, Clk, En;
output Q;
wire Y, inClk;
assign inClk = ~Clk;
dFlipFlop first (.D(D), .Clk(Clk), .En(En), .Q(Y));
dFlipFlop second (.D(Y), .Clk(inClk), .En(En), .Q(Q));
endmodule
dflipflop.v (My Testbench)
`include "methods.v"
module masterSlaveTest();
reg D, Clk, En, Q;
initial begin
$monitor(D, Clk, En, Q);
D = 1;
Clk = 1;
En = 0;
#5 $finish;
end
always begin
#5 Clk = ~Clk;
end
endmodule
