Error: Iteration limit 5000 reached at time xxx ns

Question

I was reading the book "Verilog Hdl" by Samir Palnitkar. At the end of chapter 6 there is this exercise: design a synchronous counter using master-slave JK flip-flops. However I am struggling with the JK flip-flop part. Here's the JK flip-flop circuit provided in the book:

And here's my Verilog code for the above circuit (I have checked it multiple times, hopefully there's no stupid mistake):

module test(in1, in2, clk, out, clr);
    input in1, in2, clk, clr;
    output out;

    mJKff wtf(
        .Q(out),
        .J(in1),
        .K(in2),
        .clk(clk),
        .clr(clr));

endmodule

module mJKff(Q, J, K, clk, clr);
    output Q;
    input J, K, clk, clr;

    wire
        a, b, c, d, y, ybar, cbar, qbar;

    assign
        a    = ~(qbar & J & clk & clr),
        b     = ~(clk & K & Q),
        y     = ~(a & ybar),
        ybar = ~(y & clr & b),
        c    = ~(y & cbar),
        d    = ~(ybar & cbar),
        cbar = ~clk;

    assign
        qbar = ~(Q & clr & d),
        Q    = ~(c & qbar);

endmodule

The code compiled successfully, I use Quartus Prime v18.0 for simulation and get this error:

Error (suppressible): (vsim-3601) Iteration limit 5000 reached at time xxx ns.

"xxx" is exactly at the moment when 'clk' is rising and J = 1; K = 0; clr = 1 What's wrong?

Unn Unn · Accepted Answer · 2018-09-01T02:21:37

You need to add delays in your circuit; without them the loops in your logic run infinitely in simulation; example:

assign #1 qbar = ~(Q & clr & d);

Error: Iteration limit 5000 reached at time xxx ns

1 Answers