Creating a JK Flip Flop module using an SR Flip Flop Module in Verilog

Question

I have written verilog modules for SR Latch, SR Flip Flop (by instantiating the SR Latch module), and JK Flip Flop (by instantiating the SR Latch module). I'm using Xilinx Vivado 2019 version for simulation and viewing output waveforms. The SR Latch and SR Flip flop modules work just fine and I'm getting the proper output waveforms also. I tried creating a JK Flip Flop Module by instantiating the SR Latch Module. But I just don't get the output waveforms. I don't know what is going wrong. I checked the Boolean expressions as well. Everything seems to be fine. Can someone please point out the error?

Here are the codes.

SR Latch Module

module sr_latch(s, r, q, qbar);
    input s, r;
    output q, qbar;
    nand(q, s, qbar);
    nand(qbar, r, q);
endmodule

SR Flip Flop Module using the SR Latch

module sr_ff(s, r, clk, q, qbar);
    input s, r, clk;
    output q, qbar;
    reg t1, t2;
    always @(posedge clk)
        begin
            t1 <= !(clk & s);
            t2 <= !(clk & r);
        end
    sr_latch SRL(t1, t2, q, qbar);
endmodule

JK Flip Flop using SR Latch

module jk_ff(j, k, clk, q, qbar);
    input j, k, clk;
    output q, qbar;
    reg t1, t2;
    always @(posedge clk)
        begin
            t1 <= !(clk & qbar & j);
            t2 <= !(clk & q & k);
        end
    sr_latch SRL(t2, t1, q, qbar);
endmodule

JK Flip Flop Testbench

module jk_ff_tb();
    wire q, qbar;
    reg j, k, clk=1;
    integer i;
    jk_ff JKFF(j, k, clk, q, qbar);
    always #25 clk = !clk;

    initial
        begin
            for(i=0; i<4; i=i+1)
                begin
                    {j, k} <= i; #50;
                end
        $stop;
        end
endmodule

maybe because JK_ff has nothing go do with jk_ff. Also, do not use clk & in your flop expressions. — Serge
@Serge Why not? Had I instantiated the SR Flip Flop module, there wouldn't be any need for clk & . But I'm instantiating an SR Latch. So, I must use clk &. — Aditya
The Hardware Design Community doesn't seem to be very active here. I posted this question nearly 12 hours back and my Question has just 13 views! Is there any platform to get in touch with the community? — Aditya
this forum is not a hardware design community, it is about programming. Your clk& statement is not needed because it is guaranteed to be '1' by the 'posedge clk'. It can also confuse synthesis tools and could make them do wrong assumptions about clocks. — Serge
@serge aah! I think you are right. It makes some sense. I will try it out and let you know — Aditya

toolic toolic · Accepted Answer · 2020-05-28T14:57:57

Your output is unknown (X) because your jk_ff model does not allow for proper initialization of the SR Latch.

Based on this simple schematic, you need to just implement the 2 NAND gates on the inputs to the SR latch:

This is one way, using continuous assignments:

module jk_ff (j, k, clk, q, qbar);
    input j, k, clk;
    output q, qbar;
    wire sn = clk & qbar & j;
    wire rn = clk & q    & k;
    sr_latch SRL (sn, rn, q, qbar);
endmodule

This allows the output to become known.

Another way is to add 2 nand primitives.

Note that the JK Flip-flop can be constructed from an SR Latch, not an SR Flip-flop.

Creating a JK Flip Flop module using an SR Flip Flop Module in Verilog

1 Answers