VHDL unexpected behaviour of XNOR for std_logic_vector

Question

I have a series of 25 64bit std_logic_vectors in my structural VHDL code. These should always be identical and I want to test if there are any faults which flip a bit. My code looks like this:

outX <= mt1_op XNOR mr2_op XNOR mt3_op XNOR .... XNOR mt25_op;

This gives me no errors and synthesises fine, but when I simulate it in ISim, the XNOR operation does not seem to be working. I expect all 1s or the occasional 0 if there is a fault, but the final output signal, outX, simply has the same value as all of the input signals. I won't bother stating the entire 64bit vector but as an unsigned int it resolves to 7776. All of the input vectors are the same - 7776 - and when I XNOR them all together, I get an answer of 7776.

I suspect that the problem might be caused by the XNOR operations being applied one at a time, i.e.

OutX <= (mt1_op XNOR mt2_op XNOR(mt3_op XNOR(mt4_op XNOR( ..... )))))))));

which will not give the desired behaviour.

Does anyone have an idea how I can get the behaviour that I want? i.e. if all 25 vectors are identical, give me all 1s or where there are differences, give me a 0. ??

Thanks

Tom

Morten Zilmer Morten Zilmer · Accepted Answer · 2015-03-16T15:40:35

The XNOR expression is working just fine:

'0' XNOR '0' XNOR ... XNOR '0' = '0'  -- For 25 XNOR '0's
'1' XNOR '1' XNOR ... XNOR '1' = '1'  -- For 25 XNOR '1's

So the expression will return the argument vector if the same vector is given 25 times to XNOR.

To check if all vectors are identical you can do:

or_all <= mt1_op OR mt2_op OR ... OR mt25_op;    
and_all <= mt1_op AND mt2_op AND ... AND mt25_op; 
identical <= or_all = and_all;  -- Boolean as resulting type

And for resulting type as std_logic

identical_std_logic <= '1' when (and_all = or_all) else '0';

VHDL unexpected behaviour of XNOR for std_logic_vector

1 Answers