How do I concatenate parameters and integers in verilog

Question

My code for an Altera FPGA has 8 memories, that I need to initialise using memory initialization files (mifs). To enable me to instantiate memories with different mifs, I make the following changes to the memory definition file.

original code

module my_memory (
input clk,addr,din,wen,ren;
output dout);
...
...
defparam
altsyncram_component.init_file = "memory_init.mif";
...
endmodule

modified code

module my_memory (
input clk,addr,din,wen,ren;
output dout
);


parameter MIFNAME = "memory_init.mif";

...
...
...
defparam
altsyncram_component.init_file = MIFNAME,
...
endmodule

This now allows me to instantiate multiple memory blocks and pass the initialisation file as a parameter.

My memory instantiation now looks like this

my_memory #(.MIFNAME("mem_0_init.mif") u_mem0 (...);
my_memory #(.MIFNAME("mem_1_init.mif") u_mem1 (...);
my_memory #(.MIFNAME("mem_2_init.mif") u_mem2 (...);
my_memory #(.MIFNAME("mem_3_init.mif") u_mem3 (...);
my_memory #(.MIFNAME("mem_4_init.mif") u_mem4 (...);

I then decide to use a generate to instantiate my memories

generate
genvar i;
for (i=0; i<=4; i=i+1)
begin : MEM_INST
  mem_memory #(.MIFNAME({"mem_",i,"_init.mif"}) u_mem (...);
end
endgenerate

However this does not work. The memory initialisation file parameter passed to each of the instantiation is incorrect.

What do I do?

dave_59 dave_59 · Accepted Answer · 2015-02-11T00:14:08

If you can use SystemVerilog, then this is what you can write

  mem_memory #(.MIFNAME($sformatf("mem_%0d_init.mif",i)) u_mem (...);

Otherwise you will need to get creative with parameters

genvar i;
for (i=0; i<=4; i=i+1)
begin : MEM_INST
  localparam [7:0] index = "0"+i;
  mem_memory #(.MIFNAME({"mem_",index,"_init.mif"}) u_mem (...);
end
endgenerate

How do I concatenate parameters and integers in verilog

1 Answers