Verilog error expecting a description

0
votes
module controle(clock, reset, funct, opcode, overflow, PCW, PCCondW, PCDataW, PCSrc, EPCW, AluOutW, MemRegW, AluOp, AluSrcA, AluSrcB, BShift, BSrc, ShamtSrc, AW, RegW, RegDst, RegSrc, Loads, Stores, IRW, MemW, IorD, LSE);
input [5:0] opcode, funct;
input overflow, clock;
output reg AW, IRW, MemW, MemRegW, EPCW, AluOutW, PCW, PCCondW, AluSrcA,                                                     BSrc, RegW, LSE, reset;
output reg [2:0] BShift, PCDataW, Loads, PCSrc, RegSrc;
output reg [1:0] ALuSrcB, Stores, AluOp, ShamtSrc, IorD, RegDst;
parameter estado = 2'h00;
always @ (posedge clock)
begin
case(estado)
//cases
endcase
end
endmodule;

When trying to compile this code I get the following error:

Error (10170): Verilog HDL syntax error at controle.v(418) near text ";"; expecting a description

Dunno what that means.

1
verilogintel-fpgaquartus

1 Answers

2
votes

After endmodule keyword (last line) you should not use a semicolon:

module controle(...);
  ...
endmodule