segment BCD to 7 decoder in verilog

Question

I am writing a code for simulating a bcd to seven segment decoder. When i am doing so , i am getting red and blue lines in the waveform window(in Modelsim), which means that the input is not driven and the output is in undefined state. But when i running the code by forcing the values then it shows the correct results. From this i am able to figure out that the problem is in my testbench . I would rally appreciate if anybody can take a look at m code and point out what i am doing wrong. CODE

//BCD to seven segment display
module seven_segment;
reg [3:0] BCD;
wire [6:0] display;
parameter stop_time = 200;


bcd_seven n(display,BCD);       //Instantiation of the bcd to seven segment      display code

initial #stop_time $finish;

initial
begin
BCD = 0;
#10 BCD = 1;
#10 BCD = 2;
#10 BCD = 3;
#10 BCD = 4;
#10 BCD = 5;
#10 BCD = 6;
#10 BCD = 7;
#10 BCD = 8;
#10 BCD = 9;
end
initial begin
$monitor("display = %d BCD = %b",display,BCD);
end
endmodule 

//Decsription of the BCD to seven segment display
module bcd_seven(D,BCD);
output  D; 
reg [6:0] D;
input [3:0] BCD;

parameter BLANK = 7'b0000000;
parameter ZERO = 7'b1111110;
parameter ONE = 7'b0110000;
parameter TWO = 7'b1101101;
parameter THREE = 7'b1111001;
parameter FOUR = 7'b0110011;
parameter FIVE = 7'b1011011;
parameter SIX = 7'b1011111;
parameter SEVEN = 7'b1110000;
parameter EIGHT = 7'b1111111;
parameter NINE = 7'b1111011;

//I have doubt especially in this section
always @(BCD)
case(BCD)
0: D = ZERO;
1: D = ONE;
2: D = TWO;
3: D = THREE;
4: D = FOUR;
5: D = FIVE;
6: D = SIX;
7: D = SEVEN;
8: D = EIGHT;
default: D = BLANK;
endcase
endmodule

I tried to run your code. Input is driven and the output is not undefined. It seems to be okay. What behavior do you expect? — e19293001
i except the testbench to work properly and hence when i run the code i should get the desired waveforms — Abhishek Tyagi
Can u tell me what should i look for before knowing a particular code will work in a simulator, i mean can we get to know whether a particular style of writing the code will work with this simulator and not this one? — Abhishek Tyagi

Barry Moss Barry Moss · Accepted Answer · 2015-02-04T20:31:51

I did notice one bug in your code. You are missing the case statement for BCD = 9. But that wouldn't explain the other issues you are seeing.

segment BCD to 7 decoder in verilog

1 Answers