Verilog Register to output

Question

I am working with an Altera DE2 development board and I want to read an input in on the switches. This is stored in registers. Based on a counter these registers are incremented. The registers are then supposed to be output to the Seven Segment Displays thought a B2D converter. But I can not pass a register to a function.

wire [26:0] Q,Q2,Q3,Q4;
wire [3:0] one,two,three,four;
reg SecInc,MinInc,HrInc;
reg [3:0] M1,M2,H1,H2;

assign one = SW[3:0];
assign two = SW[7:4];
assign three = SW[11:8];
assign four = SW[15:12];

always begin
    M1 = SW[3:0];
    M2 = SW[7:4];
    H1 = SW[11:8];
    H2 = SW[15:12];
end

This is how I get and store the inputs. They come from the switches which we use as a binary representation on Hours and Minutes. Based on a counter we increment a minute or an hour register.

    //increment seconds from 0 to 60
counter seconds (SecInc,KEY[0],Q2);
defparam seconds.n = 8;
defparam seconds.mod = 60;

    always @ (negedge CLOCK_50) begin
      if (Q2 >= 60) begin
        MinInc = 1;
        M1 <= M1 + 1'b1;
        if(M1 >= 9) begin
          M1 <= 0;
          M2 <= M2 + 1'b1;
        end
        end else begin
          MinInc = 0;
        end
      end

We want to display the result on the SSD's.

    hex(M1,HEX4);
    hex(M2,HEX5);
    hex(H1,HEX6);
    hex(H2,HEX7);

Here in lies the problem. This is not allowed in verilog. I need a way to send my registers to a function which displays numbers from 0 to 9 using some B2D conversion.

I will say I have never had a formal intro to verilog before and I have tried all I can think to do. I even tried to make a new module in which I would pass one,two,three,four and have the module increment them, like it does with Q2 for the counter I have shown. Any suggestions or help is greatly appreciated!

As requested here is the hex module:

    module hex(BIN, SSD);
    input [15:0] BIN;
    output reg [0:6] SSD;

    always begin
      case(BIN)
        0:SSD=7'b0000001;
        1:SSD=7'b1001111;
        2:SSD=7'b0010010;
        3:SSD=7'b0000110;
        4:SSD=7'b1001100;
        5:SSD=7'b0100100;
        6:SSD=7'b0100000;
        7:SSD=7'b0001111;
        8:SSD=7'b0000000;
        9:SSD=7'b0001100;
      endcase
    end
  endmodule

Thank you in advance!

Answer 1

Your hex module is not a function, it is a module and therefore must be instantiated with an instance name like this:

hex digit0(.BIN(M1), .SSD(HEX4));
hex digit1(.BIN(M2), .SSD(HEX5));
hex digit2(.BIN(H1), .SSD(HEX6));
hex digit3(.BIN(H2), .SSD(HEX7));

Answer 2

In addition to nguthrie being correct, that you need to instantiate your hex converter as a module, you drive M1 from a race condition in your always block. Non-blocking assignments will evaluate simultaneously within a block (or essentially simultaneously). This is not a program, where things happen in order. What might work better is:

always @ (negedge CLOCK_50) begin
if (Q2 >= 60) begin
    MinInc = 1;
    if (M1 < 9) begin
        M1 <= M1 + 1'b1;
    end else begin
      M1 <= 0;
      M2 <= M2 + 1'b1;
    end
    end else begin
      MinInc = 0;
    end
end

You will also potentially get unexpected results from your blocking assignments to MinInc, but since I don't see where this is read it's hard to know what will happen. Read up on blocking (=) vs non-blocking (<=) assignments in Verilog. It's one of the trickiest concepts of the language, and misuse of the two operations is the cause of 90% of the most dastardly bugs I've ever seen. EDIT: In re-reading your question, it seems that you're trying to drive M1-4 from at least three places. You really can't have a continuous always begin block and a clocked (always @ (negedge clock) begin) driving the same register. This will send your compiler into a tantrum.