problems on simple process for writing number on seven segment display

Question

i'm beginner but still, cant believe i can't make so simple code to work. i have Digilent Nexys2 FPGA, programming xilinx ISE my goal is to print number "2" and "1" on two, different seven segment displays (i want to see "21" on it with my eyes. A,B,C,D,E,F,G,P are the leds of displays (kathodes), AN0 and AN1 are anodes of displays, 0 turns them on).

the logic i am trying to invest there, is that the FPGA will repeat this 'process' so quickly that my eye will only detect the light on. i think the reason i should put clk in process sensitivity list is that every time the clock changes, it will go into the process and execute my commands, am i right? what logical mistakes am i making here? i tried to make if else statement where IF rising_edge (clk) then "1" will be displayed else "2" but it still caused some errors.. what the heck? should i make this process clocked?

here is the warning i get when i want to synthesize it

WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. 

here are the warnings i get when i try to generate a programming bit file

WARNING:PhysDesignRules:367 - The signal <clk_IBUF> is incomplete. The signal does not drive any load pins in the design.
WARNING:Par:288 - The signal clk_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:PhysDesignRules:367 - The signal <clk_IBUF> is incomplete. The signal does not drive any load pins in the design.

and

here is the UCF- file:

NET "clk" LOC = B8;
NET "A" LOC = L18;
NET "B" LOC = F18;
NET "C" LOC = D17;
NET "D" LOC = D16;
NET "E" LOC = G14;
NET "F" LOC = J17;
NET "G" LOC = H14;
NET "P" LOC = C17;
NET "AN0" LOC = F17;
NET "AN1" LOC = H17;
NET "AN2" LOC = C18;
NET "AN3" LOC = F15;

and here comes the code itself:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity disp is
    Port ( 
        clk : in STD_LOGIC;
        A : out  STD_LOGIC;
      B : out  STD_LOGIC;
      C : out  STD_LOGIC;
      D : out  STD_LOGIC;
      E : out  STD_LOGIC;
      F : out  STD_LOGIC;
        G : out  STD_LOGIC;
        P : out  STD_LOGIC;
        AN0 : out  STD_LOGIC;
        AN1 : out  STD_LOGIC;
        AN2 : out  STD_LOGIC;
        AN3 : out  STD_LOGIC
    );
end disp;
-- main idea: writing "21" on seven segment display.
architecture BEHAV of disp is
begin
    process (clk)
    begin
        --writing '1' ( AN0 is on )
        AN0 <='0';
        AN1 <='1';
        AN2 <='1';
        AN3 <='1';
        A <='1';
        B <='0';
        C <='0';
        D <='1';
        E <='1';
        F <='1';
        G <='1';
        P <='1';
        --writing '2' ( AN1 is on )
        AN0 <='1';
        AN1 <='0';
        AN2 <='1';
        AN3 <='1';
        A <='0';
        B <='0';
        C <='1';
        D <='0';
        E <='0';
        F <='1';
        G <='0';
        P <='1';
    end process;
end BEHAV;

Answer 1

Just putting clock in the sensitivity list is not enough. You need an if statement

If rising_edge (clk) then --where all assingments here End if;

But that wouldn't be enough. You also need to figure out refresh logic for seven segment better. I don't have time otherwise I would have told you that as well.

Answer 2

So, Mr. Morten and Adeel were right. Morten's code was correct but it was 'happening' so fast that eye was not able to detect so it looked like the 2 put on 1. so i added counter, here is the code.

the speed of displaying numbers is depended on the constant 'Speed'

here is the main code itself, and waiting for your responses (what else can i do to make this simpler?)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

    entity disp is
    Port ( 
        SW : in STD_LOGIC; 
        rst : in STD_LOGIC;
        clk : in STD_LOGIC;
        led : out STD_LOGIC;
        A : out  STD_LOGIC;
        B : out  STD_LOGIC;
        C : out  STD_LOGIC;
        D : out  STD_LOGIC;
        E : out  STD_LOGIC;
        F : out  STD_LOGIC;
        G : out  STD_LOGIC;
        P : out  STD_LOGIC;
        AN0 : out  STD_LOGIC;
        AN1 : out  STD_LOGIC;
        AN2 : out  STD_LOGIC;
        AN3 : out  STD_LOGIC
    );
    end disp;

architecture BEHAV of disp is

    constant bitwidth : integer := 32; 
    constant Speed : integer := 10; 
    signal   carry : std_logic_vector (bitwidth downto 0);
    signal   counter, counter_reg : std_logic_vector (bitwidth-1 downto 0) :=(others => '0');
    constant value_one : std_logic_vector (bitwidth-1 downto 0) :="00000000000000000000000000000001";
    signal drive_an : std_logic :='0';

    component adder is
        Port ( 
            C_in : in  STD_LOGIC;
            A : in  STD_LOGIC;
            B : in  STD_LOGIC;
            C_out : out  STD_LOGIC;
            Sum : out  STD_LOGIC;
            SW : in STD_LOGIC);
    end component; 

begin

    carry(0) <= '0';
    g_counter: for N in 0 to bitwidth-1 
    generate    FOUR_ADDER: adder port map (
        C_in => carry(N),   A => counter_reg(N), B => value_one(N), C_out => carry(N+1), Sum => counter(N), SW => SW);
    end generate;     
    led <= carry(bitwidth);

    process (clk,rst) begin 
        if rst = '1' then 
            counter_reg <= (others => '0'); 
        elsif rising_edge(clk) then
            counter_reg <= counter; 
            if counter_reg (Speed)= '1' then
                drive_an <= not drive_an; 
                counter_reg <= (others => '0'); 
                if drive_an = '0' then
                    AN0 <= '0';         
                    AN1 <= '1';         
                    AN2 <= '1';         
                    AN3 <= '1';         
                    A   <= '1';         
                    B   <= '0'; 
                    C   <= '0';         
                    D   <= '1';         
                    E   <= '1';         
                    F   <= '1';         
                    G   <= '1';         
                    P   <= '1';
                else
                    AN0 <= '1';         
                    AN1 <= '0';         
                    AN2 <= '1';         
                    AN3 <= '1';         
                    A   <= '0';         
                    B   <= '0';         
                    C   <= '1';         
                    D   <= '0';         
                    E   <= '0';         
                    F   <= '1';         
                    G   <= '0';         
                    P   <= '1';
                end if;
            end if;     
        end if;
    end process; 
end BEHAV;

and if someone will ever need to test it: here is the code for adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adder is
    Port ( 
        C_in : in  STD_LOGIC;
        A : in  STD_LOGIC;
        B : in  STD_LOGIC;
        C_out : out  STD_LOGIC;       
        Sum : out  STD_LOGIC;     
        SW : in STD_LOGIC
    );
end adder;


architecture Behavioral of adder is
begin
    Sum <= C_in xor (a xor (b xor SW));
    C_out <= (a and (b xor SW)) or (C_in and (a xor (b xor SW)));
end Behavioral;

here is the UCF file

NET "clk" LOC = B8;
NET "A" LOC = L18;
NET "B" LOC = F18;
NET "C" LOC = D17;
NET "D" LOC = D16;
NET "E" LOC = G14;
NET "F" LOC = J17;
NET "G" LOC = H14;
NET "P" LOC = C17;
NET "AN0" LOC = F17;
NET "AN1" LOC = H17;
NET "AN2" LOC = C18;
NET "AN3" LOC = F15;
NET "led" LOC = J14;