frequency divider in Verilog with JK Flip-Flop

Question

this my JK_FF code :

module JK_FF(j,k,clk,Q);

input j,k,clk;
output reg Q;

always @(posedge clk)
begin
    if (j==0 && k==0)
        Q=Q;
    else if (j==0 && k==1)
        Q=0;
    else if (j==1 && k==0)
        Q=1;
    else
        Q=~Q;   
end
endmodule

And this is my frequency divider

module freqDivider(clk,Q);
input clk;
output reg Q;
reg j2;

JK_FF f1(.j(~Q),.k(0),.clk(clk),.Q(j2));
JK_FF f2(.j(j2),.k(0),.clk(clk),.Q(Q));


endmodule

this is the circuit:

enter image description here

Output is not correct , it's always 1:

enter image description here

what's wrong with my code ?

EDIT AFTER ANSWERS (SOLVED):

So silly mistake , confusing VCC with JND !! i change .k(0) to .k(1), and result : enter image description here

What does your testbench look like? How is internal signal j2 behaving? Why are the k connections different between your module and your schematic? — user1619508
@JoeHass O !!! :-O !! Your right , i confused VCC with JND :-O !! what can i do now ? should i remove my question ??!! so silly question!! :(( :'( thanks by the way Joe ;) if i change .k(0) to .k(1) is it all like schematic ? — Omid Yaghoubi
@DEopen, k should be connected as .k(1'b1). .k(1) will give the correct result but should give an width miss match warning as it infers .k(32'd1) (a 32bit input connecting to a 1bit port). It is recommended to use explicit widths and radix everywhere in your design. — Greg
you should use nonblocking statements in always blocks used to model flip flops. asic-world.com/tidbits/blocking.html — Eric Cope

Morgan Morgan · Accepted Answer · 2014-05-27T14:13:49

With a JK-FlipFlop, and k tied to 0 you can only ever set the output or maintain state.

A JK state table is:

J  K | Q
--------
0  0 | Q  (Maintain)
0  1 | 0  (Reset)
1  0 | 1  (Set)
1  1 | ~Q (Toggle)

Tying k to 0 you now have:

J  K | Q
--------
0  0 | Q  (Maintain)
1  0 | 1  (Set)

Which is why once your output reaches 1 it stays there.

A digital frequency divider can easily be done with standard D-Types though. Actually a good little animation on wikipedia. Or another site here.

Basically each flop connects D to Q_BAR. and Q_BAR becomes the clock to the next stage.

frequency divider in Verilog with JK Flip-Flop

1 Answers