I can't figure out how to take the absolute value of two std_logic_vector(31 downto 0);
here is an example of the code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- for the signed, unsigned types and arithmetic ops
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
...
...
port (
X: in std_logic_vector(31 downto 0);
Y: in std_logic_vector(31 downto 0);
F: out std_logic_vector(31 downto 0)
);
..
..
..
process(X,Y)
begin
F <= abs(X-Y) --this doesnt work
abs
on the standardsigned
type will often synthesize to better code in many FPGA and ASIC vendor's synthesizers which special case some built-in math operations. – wjl