Can't have a simulation for my VHDL code

Question

I'm looking after a reason or an answer for my problem which is : My VHDL code is working, i'm trying to create a frequency divider by 10. The problem is that the simulation report keep giving me an undefined output(no value).

This is my VHDL code, I'd be so grateful for any help! Thank You!

Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity Frequency_divider is 
port(clk: in std_logic;
     Q:out std_logic);
end Frequency_divider;

architecture desc_freq_divider_10 of Frequency_divider is 


signal S: std_logic:='0';
begin

process(clk,S)
    variable cpt: integer:=0;
    begin

        if (rising_edge(clk)) then 
            cpt:=cpt+1;
        end if;

        if (cpt=5) then 
            S<=not(S);
            cpt:=0;
        end if;

    end process;    
    Q<=S;
end desc_freq_divider_10;       

Answer 1

I got rid of the extraneous use clauses:

--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;

Added a test bench:

library ieee;
use ieee.std_logic_1164.all;

entity freq_test is
end entity;

architecture tb of freq_test is
    signal CLK:     std_logic :='0';
    signal Q:       std_logic;
begin

CLOCK:
    process
    begin
        if Now < 300 ns then
            wait for 10 ns;
            clk <= not clk;
        else
            wait;
        end if;
    end process;
DUT:
    entity work.frequency_divider
        port map (clk,q);
end architecture;

Analyzed all of it, elaborated and simulated and got it to work.

It says your code is functional and that you have a tool chain usage error more than likely.

Answer 2

Simulation should be fine, as David Koontz describes, but for a synthesizable design the process should have only clk in sensitivity list, and should have all updates in the if statement like:

process(clk)
  variable cpt : integer range 0 to 5 := 0;  -- Must be constrained for synthesis
begin
  if (rising_edge(clk)) then
    cpt := cpt+1;
    if (cpt = 5) then
      S   <= not(S);
      cpt := 0;
    end if;
  end if;
end process;

The other design is likely to infer latches and similar issues.

2014-02-17 edit: Added constrain on cpt integer, since synthesis can't figure out minimal size, thus will make too many flip-flops.