port map in structural VHDL code

Question

I have the following code for a structural modeling in VHDL. When I try to compile it (ghdl -a filename.vhdl), I get this error in the 4 lines commented below: "<=" or ":=" expected instead of port

BTW, I had already defined the components used before the code block below.

What's wrong with my code? Am I not allowed to use port map inside a process/if-statement?

What can I do to fix this? Thanks!

-- Entity Definition
entity jk is
    port(
        CP: in std_logic; -- clock signal
        J : in std_logic; -- J signal
        K : in std_logic; -- K signal
        Q : inout std_logic; -- Q signal
        QN : inout std_logic; -- Q' signal
        reset : in std_logic -- reset signal
    );
end entity jk;

architecture dev1 of jk is

    -- declare the singals that outputs the results of some gates
    signal a, b, internal_q, internal_qn : std_logic;

    -- get each component needed
    component and3 is
        port(o0 : out std_logic; i0, i1, i2: in std_logic);
    end component and3;
    component nor2 is
        port(o0 : out std_logic; i0, i1: in std_logic);
    end component nor2;

begin

    internal_q <= Q;    -- used to show internal Q value
    QN <= not Q;        -- inverse of Q
    internal_qn <= QN;  -- used to show internal QN value

    process is
    begin
        if (reset = '0') then -- asynchronous reset
            Q <= '0';
            internal_qn <= '0';
        elsif rising_edge(CP) then -- on positive clock edge
            -- AND gate outputs
            g0: and3 port map(a, internal_q, K, CP); -- error
            g1: and3 port map(b, internal_qn, J, CP); - error

            -- NOR gate outputs
            g2: nor2 port map(Q, a, internal_qn); -error
            g3: nor2 port map(QN, b, internal_q); -error
        end if;
    end process;

end architecture dev2;

Russell Russell · Accepted Answer · 2014-01-16T14:38:34

No, you are not allowed to instantiate components (use port maps) inside of a process.

You should be instantiating your components below the begin statement of your architecture. Wire them up there appropriately. Your process should drive all of the registered logic. I actually don't see any need for a process statement at all in this code. Since all of your inputs are coming from your entity (I assume) then you really don't need to do any registered logic in this file.

Can you post your entity as well? I cannot see where signals J and K and CP and Q and QN are being defined.

port map in structural VHDL code

1 Answers