why cant I use XNOR on type "std_logic_vector" ?

Question

it seems straightforward but I cant get past it

            din : in std_logic_vector(13 downto 0);
            sin : in std_logic_vector(3 downto 0);
            .
            .
            .

            if ( din(idx downto idx-3) XNOR sin(3 downto 0) ) then

and I get the

** Error: Z:/lab_dig_2/1/prep/additionalQ/additionalQ.vhd(30): Type error resolving infix expression "xnor" as type std.STANDARD.BOOLEAN.

error

is there a special operator for vectors? I remember that std_logic_vector is a perfect type for this kind of operators?

Morten Zilmer Morten Zilmer · Accepted Answer · 2013-12-04T11:06:26

The xnor in your expression operates on two std_logic_vector type and thus returns another std_logic_vector type, but the if expression expects a boolean type.

You may want to change the expression to the below, if you want a condition that is true when the xnor result is not all zeros:

if (din(idx downto idx-3) XNOR sin(3 downto 0)) /= "0000" then

EDIT: More information about implicit type convert in VHDL-2008

VHDL is a strong typed language where the designer typically has to do explicit type casts so the result matches the required type, and otherwise an error is generated.

However, VHDL-2008 has added some implicit type casting, in special with the condition operator ?? which can convert to boolean type. The operator is declared in std_logic_1164 system package as:

function "??" (l : std_ulogic) return boolean;

The condition operation is automatically applied for if, elsif, until, assert, and similar places if the expression did not evaluate to a boolean type. So, if you are using VHDL-2008, then it is possible to write:

signal test_sl : std_logic;
...
if test_sl then
  ...

Whereby the condition operator ?? is implicitly applied, as if written:

if ?? test_sl then

An equivalent to the below, which is also valid in VHDL-2002:

if (test_sl = '1') or (test_sl = 'H') then

The ?? operator is only declared in standard VHDL-2008 for std_ulogic type, which thus also applies to std_logic type. However, the operator can be overloaded in a user declared function to apply for std_logic_vector, with:

-- Or operation of ?? for all elements in arg
function "??" (arg : std_ulogic_vector) return boolean is
  variable res_v : boolean;
begin
  res_v := FALSE;
  for idx in arg'range loop
    res_v := res_v or (?? arg(idx));
  end loop;
  return res_v;
end function;

If the above is declared, then it is possible to use implicit casting of std_logic_vector to boolean in if statements, like:

signal test_slv : std_logic_vector(3 downto 0);
...
if test_slv then
  ....

Or even:

if din(idx downto idx-3) XNOR sin(3 downto 0) then

A word of caution though, since the code may be become less readable to others and thus more error prone, if such tricks are used; but it is possible.

why cant I use XNOR on type "std_logic_vector" ?

1 Answers